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| 型号： | WJLXT972ALC.A4-857345 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 38/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT972ALC.A4-857345 |
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Page 43
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.9 Monitoring Operations
If the Link Integrity Test function is disabled (which can be done by setting
Configuration register bit 16.14 to ‘1’), the LXT972A PHY transmits to the connection
regardless of detected link pulses.
5.8.5
Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop
being received. If this condition occurs, the LXT972A PHY returns to the auto-negotiation
phase if auto-negotiation is enabled. If the Link Integrity Test function is disabled by
setting Configuration register bit 16.14 to ‘1’, the LXT972A PHY transmits packets,
regardless of link status.
5.8.6
10BASE-T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the
LXT972A PHY. To enable this function, set register bit 16.9 = 1. When this function is
enabled, the LXT972A PHY asserts its COL output for 5 to 15 bit times (BT) after each
packet. For SQE timing parameters, see Figure 26, 10BASE-T SQE (Heartbeat) Timing,
5.8.7
10BASE-T Jabber
If a transmission exceeds the jabber timer, the LXT972A PHY disables the transmit and
loopback functions. For jabber timing parameters, see Figure 25, 10BASE-T Jabber and
The LXT972A PHY automatically exits jabber mode after the unjabber time has expired.
This function can be disabled by setting register bit 16.10 = 1.
5.8.8
10BASE-T Polarity Correction
The LXT972A PHY automatically detects and corrects for the condition in which the
receive signal (TPIP/N) is inverted. Reversed polarity is detected if eight inverted link
pulses, or four inverted end-of-frame (EOF) markers, are received consecutively. If link
pulses or data are not received by the maximum receive time-out period (96 to 128 ms),
the polarity state is reset to a non-inverted state.
When polarity reversal is detected in 10BASE-T operation, register 17.5 is set to 1. (For
details, see bit 17.5 in Table 50, Status Register #2 - Address 17, Hex 11, on page 72.)
5.9
Monitoring Operations
5.9.1
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
register bit 17.7 is set to ‘1’ once the auto-negotiation process is completed.
register bits 1.2 and 17.10 are set to ‘1’ once the link is established.
register bits 17.14 and 17.9 can be used to determine the link operating conditions
(speed and duplex).
Note:
When the LXT972A PHY detects incorrect polarity for a 10BASE-T operation, register bit
17.5 is set to ‘1’.
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