参数资料
型号: WJLXT972ALC.A4
厂商: CORTINA SYSTEMS INC
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 13/97页
文件大小: 1281K
代理商: WJLXT972ALC.A4
Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
20
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
Table 8 lists signal descriptions of the LXT972A Transceiver configuration and LED driver pins.
Note:
Pull-up/pull-down resistors of 10k Ohms can be implemented if LEDs are not used in the design.
Table 8.
Intel LXT972A Transceiver Configuration and LED Driver Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
5
6
TxSLEW0
TxSLEW1
I
Tx Output Slew Controls 0 and 1.
These pins select the TX output slew rate (rise and fall time)
as follows:
TxSLEW1
TxSLEW0
Slew Rate (Rise and Fall Time)
0
3.0 ns
0
1
3.4 ns
1
0
3.9 ns
1
4.4 ns
4
RESET_L
I
Reset.
This active Low input is ORed with the control register Reset
bit (Register bit 0.15). The transceiver reset cycle is extended
to 258
μs (nominal) after reset is de-asserted.
17
RBIAS
AI
Reference Current Bias.
This pin provides bias current for the internal circuitry. Must
be tied to ground through a 22.1 k
Ω, 1% resistor.
33
PAUSE
I
Pause.
When set High, the transceiver advertises Pause capabilities
during auto-negotiation.
39
PWRDWN
I
Power Down.
When set High, this pin puts the transceiver in a power-down
mode.
1
2
REFCLK/XI
XO
I and
O
Reference Clock Input / Crystal Input and Crystal Output.
A 25 MHz crystal oscillator circuit can be connected across XI
and XO. A clock can also be used at XI. Refer to Section
Description section.
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3
I/O
LED Drivers 1-3.
These pins drive LED indicators. Each LED can display one
of several available status conditions as selected by the LED
Configuration Register. (For details, see Table 55, “LED
Configuration Inputs 1-3.
These pins also provide initial configuration settings. (For
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