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| 型号： | WJLXT972ALC.A4SE000 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 12/100页 |
| 文件大小： | 1046K |
| 代理商： | WJLXT972ALC.A4SE000 |
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Datasheet
19
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
When the LXT972A receives a Remote Fault indication from its partner during auto-negotiation it
does the following:
Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and
Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the
local controller.
3.2.2
MII Data Interface
The LXT972A supports a standard Media Independent Interface (MII). The MII consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT972A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and
receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically,
once the operating conditions of the network link have been determined. Refer to “MII Operation”
on page 26 for additional details.
3.2.2.1
Increased MII Drive Strength
A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive
signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or
through a connector. The MII drive strength in the LXT971A can be increased by setting Register
bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO
interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a
higher drive strength.
3.2.3
Configuration Management Interface
The LXT972A provides both an MDIO interface and a Hardware Control Interface for device
configuration and management.
3.2.3.1
MDIO Management Interface
The LXT972A supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972A. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972A also supports additional registers for expanded functionality. The LXT972A supports
multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using
an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT972ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4SE000 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
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| WJM1000 | 功能描述:射频模块 902-928 MHz US ISM EPC Class 1 Gen 2 RoHS:否 制造商:Linx Technologies 产品:Transceiver Modules 频带:902 MHz to 928 MHz 输出功率:- 15.5 dBm to + 12.5 dBm 接口类型:UART 工作电源电压:- 0.3 VDC to + 5.5 VDC 传输供电电流:38.1 mA 接收供电电流:22.7 mA 天线连接器类型:U.FL 最大工作温度:+ 85 C 尺寸:1.15 mm x 0.63 mm x 0.131 mm |
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