- 您现在的位置：买卖IC网 > PDF目录68583 > WJLXT972ALC.A4SE000 (INTEL CORP) DATACOM, ETHERNET TRANSCEIVER, PQFP64 PDF资料下载
参数资料
| 型号： | WJLXT972ALC.A4SE000 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 18/100页 |
| 文件大小： | 1046K |
| 代理商： | WJLXT972ALC.A4SE000 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
24
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
3.4.3.2
Software Power Down
Software power-down control is provided by bit 0.11 in the Control Register (refer to Table 39 on
page 60). During soft power-down, the following conditions are true:
The network port is shut down.
The MDIO registers remain accessible.
3.4.4
Reset
The LXT972A provides both hardware and software resets. Configuration control of auto-
negotiation, speed, and duplex mode selection is handled differently for each. During a hardware
reset, auto-negotiation and speed are read in from pins (refer to Table 9 on page 25 for pin settings
and to Table 39 on page 60 for register bit definitions).
During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values
made since the last hardware reset are not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).
3.4.5
Hardware Configuration Settings
The LXT972A provides a hardware option to set the initial device configuration. The hardware
option uses the three LED driver pins. This provides three control bits, as listed in Table 9. The
LED drivers can operate as either open-drain or open-source circuits as shown in Figure 7.
.
Figure 7. Hardware Configuration Settings
Configuration Bit = 1
Configuration Bit = 0
LED/CFG Pin
3.3 V
1. The LED/CFG pins automatically adjust their
polarity upon power-up or reset.
2. Unused LEDs may be implemented with pull-up/
pull-down resistors of 10 K.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT972ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4SE000 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT972MLC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| WJLXT972MLC.A4 S L7U9 | 制造商:Intel 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| WJLXT972MLC.A4-864115 | 功能描述:TXRX ETH 10/100 SGL PORT 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
| WJLXT972MLCA4 | 制造商:Cortina Systems Inc 功能描述: |
| WJM1000 | 功能描述:射频模块 902-928 MHz US ISM EPC Class 1 Gen 2 RoHS:否 制造商:Linx Technologies 产品:Transceiver Modules 频带:902 MHz to 928 MHz 输出功率:- 15.5 dBm to + 12.5 dBm 接口类型:UART 工作电源电压:- 0.3 VDC to + 5.5 VDC 传输供电电流:38.1 mA 接收供电电流:22.7 mA 天线连接器类型:U.FL 最大工作温度:+ 85 C 尺寸:1.15 mm x 0.63 mm x 0.131 mm |
发布紧急采购，3分钟左右您将得到回复。