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参数资料
| 型号： | WV3EG64M72ETSU335D3M |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 6/10页 |
| 文件大小： | 230K |
| 代理商： | WV3EG64M72ETSU335D3M |
White Electronic Designs
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
Octobert 2005
Rev. 0
PRELIMINARY
WV3EG64M72ETSU-D3
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C
≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5
Unit
Operating current
IDD0*
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN);
DQ, DM and DQS inputs change once per clock cycle; Address and control
inputs change once every two clock cycles
945
mA
Operating current
IDD1*
One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN);
IOUT = 0mA; Address and control inputs change once per clock cycle
1215
mA
Percharge power-
down standby current
IDD2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW
45
mA
Idle standby current
IDD2F**
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address
and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS and DM
270
mA
Active power-down
standby current
IDD3P**
One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW
270
mA
Active standby
current
IDD3N**
CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX);
tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address
and other control inputs changing once per clock cycle
405
mA
Operating current
IDD4R*
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA
1260
mA
Operating current
IDD4W*
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and
DQS inputs change twice per clock cycle
1350
mA
Auto refresh current
IDD5**
tRC = tRFC(MIN)
1845
mA
Self refresh current
IDD6**
CKE < 0.2V
45
mA
Orerating current
IDD7*
Four device bank interleaving Reads Burst = 4 with auto precharge;
tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during
Active READ, or WRITE commands
3240
mA
Note: These specications apply to modules built with Samsung components only.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WV3EG64M72ETSU-D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| WV3EG72M64ETSU335D3MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| WV3EG72M64ETSU335D3SG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| WV3H2256M72AER403D6IMG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL |
| WV3H2256M72AER403D6ISG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL |
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