参数资料
型号: WV3EG64M72ETSU335D3M
厂商: WHITE ELECTRONIC DESIGNS CORP
元件分类: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, DMA184
封装: DIMM-184
文件页数: 8/10页
文件大小: 230K
代理商: WV3EG64M72ETSU335D3M
White Electronic Designs
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
October 2005
Rev. 0
PRELIMINARY
WV3EG64M72ETSU-D3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Parameter
Symbol
335
Unit
Min
Max
Mode register set cycle time
tMRD
12
ns
DQ & DM setup time to DQS
tDS
0.45
ns
DQ & DM hold time to DQS
tDH
0.45
ns
Control & Address input pulse width
tIPW
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
ns
Exit self refresh to non-Read command
tXSNR
75
ns
Exit self refresh to read command
tXSRD
200
tCK
Refresh interval time
tREFI
7.8
us
Output DQS valid window
tQH
tHP-tQHS
—ns
Clock half period
tHP
tCLmin or tCHmin
—ns
Data hold skew factor
tQHS
0.55
ns
DQS write postamble time
tWPST
0.4
0.6
ns
Active to Read with Auto precharge command
tRAP
18
Autoprecharge write recovery + Precharge time
tRAL
(tWR/tCK) +
(tRP/tCK)
tCK
Note: These specications apply to modules built with Samsung components only.
AC OPERATING TEST CONDITIONS
VCC = 2.5V, VCCQ = 2.5V, 0°C
≤ TA ≤ 70°C
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage
VIH(AC)
VREF +0.31
V
1
Input Low (Logic 0) Voltage
VIL(AC)
VREF -0.31
V
1
Input Differential Voltage, CK and CK# inputs
VID(AC)
0.7
VCCQ+0.6
V
Input Crossing Point Voltage, CK and CK# inputs
VIX(AC)
0.5*VCCQ-0.2
0.5*VCCQ+0.2
V
NOTES:
1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
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WV3EG64M72ETSU335D3SG 64M X 72 DDR DRAM MODULE, DMA184
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