参数资料
型号: X1205V8IZT1
厂商: Intersil
文件页数: 5/22页
文件大小: 0K
描述: IC RTC/CALENDAR 2-WIRE 8-TSSOP
标准包装: 2,500
类型: 时钟/日历
特点: 警报器,闰年
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 2.7 V ~ 5.5 V
电压 - 电源,电池: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 带卷 (TR)
13
FN8097.3
May 2, 2006
Figure 4. Valid Data Changes on the SDA Bus
Figure 5. Valid Start and Stop Conditions
Figure 6. Acknowledge Response From Receiver
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 7.
After loading the entire Slave Address Byte from the
SDA bus, the X1205 compares the device identifier
and device select bits with ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the
SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0H,
so a current address read of the CCR array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 7.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. For a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
SCL
SDA
Data Stable
Data Change
Data Stable
SCL
SDA
Start
Stop
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
X1205
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