参数资料
型号: X4005M8I
厂商: Intersil
文件页数: 3/16页
文件大小: 0K
描述: IC SUPERVISOR CPU I2C 8-MSOP
标准包装: 80
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 高有效
复位超时: 最小为 100 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 管件
X4003, X4005
Ordering Information (Continued)
PART NUMBER
PART NUMBER
RESET
PART
RESET
PART
V CC RANGE V TRIP RANGE TEMP. RANGE
(ACTIVE LOW)
X4003S8I-2.7A
MARKING
X4003 AP
(ACTIVE HIGH)
X4005S8I-2.7A
MARKING
X4005 AP
(V)
2.7 to 3.6
(V)
2.85 to 3.0
(°C)
-40 to +85
PACKAGE
8 Ld SOIC
PKG. DWG. #
MDP0027
(150 mil)
X4003S8IZ-2.7A
(Note)
X4003 ZAP X4005S8IZ-2.7A X4005 ZAP
(Note)
-40 to +85
8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4003M8I-2.7A
ACM
X4005M8I-2.7A
ACV
-40 to +85
8 Ld MSOP
M8.118
(3.0mm)
X4003M8IZ-2.7A
DAC
X4005M8IZ-2.7A DAL
-40 to +85
8 Ld MSOP
M8.118
(Note)
(Note)
(3.0mm) (Pb-free)
X4003S8I-2.7
X4003 G
X4005S8I-2.7
X4005 G
2.55 to 2.7
-40 to +85
8 Ld SOIC
MDP0027
(150 mil)
X4003S8IZ-2.7
X4003 ZG
X4005S8IZ-2.7
X4005 ZG
-40 to +85
8 Ld SOIC
MDP0027
(Note)
(Note)
(150 mil) (Pb-free)
X4003M8I-2.7
ACO
X4005M8I-2.7
ACX
-40 to +85
8 Ld MSOP
M8.118
(3.0mm)
X4003M8IZ-2.7
DAB
X4005M8IZ-2.7
DAK
-40 to +85
8 Ld MSOP
M8.118
(Note)
(Note)
(3.0mm) (Pb-free)
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
Pin Descriptions
PIN
NUMBER
(MSOP)
1
2
3
4
5
6
7
8
NAME
NC
NC
RESET/RESET
V SS
SDA
SCL
WP
V CC
FUNCTION
No internal connections
No internal connections
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V CC falls below
the minimum V CC sense level. It will remain active until V CC rises above the minimum V CC sense level for 250ms.
RESET/RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the
selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a
stop condition resets the watchdog timer. RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop
condition resets the watchdog timer. The absence of this procedure within the watchdog time-out period results in
RESET/RESET going active.
Serial Clock. The serial clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH prevents changes to the watchdog timer setting.
Supply voltage
3
FN8113.2
June 30, 2008
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