参数资料
型号: X40410V8-B
厂商: Intersil
文件页数: 12/24页
文件大小: 0K
描述: IC VOLTAGE MON DUAL W/SUP 8TSSOP
标准包装: 100
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 可调节/可选择
电压 - 阀值: 2.6V,4.4V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
X40410, X40411, X40414, X40415
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF hex
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
General Purpose Memory Array Configuration
Memory Address
A8:A0
000h
needs to read, but is not ready for the data.
0FFh
Lower 256 bytes
Sequential Read
Sequential reads can be initiated as either a current
100h
1FFh
Upper 256 bytes
Block Protect Option
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000 H and the device continues to out-
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 13. X40410/11 Addressing
Slave Byte
put data for each acknowledge received. See Figure 15
General Purpose Memory
1
0
1
0
0
0
A8 R/W
for the acknowledge and data transfer sequence.
Control Register
Fault Detection Register
1
1
0
0
1
1
1
1
0
0
0
0
1
0
R/W
R/W
SERIAL DEVICE ADDRESSING
Word Address
Memory Address Map
General Purpose Memory A7
A6 A5 A4 A3 A2 A1
A0
CR, Control Register, CR7: CR0
Address: 1FF hex
Control Register
Fault Detection Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 14. Current Address Read Sequence
S
Signals from
the Master
SDA Bus
t
a
r
t
Slave
Address
1 0 1 0 0 0
1
S
t
o
p
Signals from
12
the Slave
Data
FN8116.0
March 28, 2005
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