参数资料
| 型号： | X40420S14I-CT1 |
| 厂商： | Intersil |
| 文件页数： | 7/25页 |
| 文件大小： | 0K |
| 描述： | IC VOLT MON DUAL SUP/SW 14-SOIC |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.6V，2.9V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 带卷 (TR) |
X40420, X40421
Resetting the V TRIPx Voltage
To reset a V TRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V TRIP1 and 0Bh for V TRIP2 , followed by 00h for the Data
Byte in order to reset V TRIPx . The STOP bit following a
valid write operation initiates the programming sequence.
Condition
V CC > V TRIP1
V CC > V TRIP1 &
V BATT = 0
0 ≤ V CC ≤ V TRIP1
and V CC < V BATT
Mode of Operation
Normal Operation
Normal Operation without battery
backup capability
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
Pin WDO must then be brought LOW to complete the
operation.
After being reset, the value of V TRIPx becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the memory array.
System Battery Switch
As long as V CC exceeds the low voltage detect threshold
V TRIP , V OUT is connected to V CC through a 5 ? (typical)
switch. When the V CC has fallen below V1 TRIP , then V CC
is applied to V OUT if V CC is or equal to or greater than
V BATT - 0.03V. When V CC drops to less than V BATT -
0.03V, then V OUT is connected to V BATT through an 80 ?
(typical) switch. V OUT typically supplies the system static
RAM voltage, so the switchover circuit operates to pro-
tect the contents of the static RAM during a power failure.
Typically, when V CC has failed, the SRAMs go into a
lower power state and draw much less current than in
their active mode. When V CC returns, V OUT switches
back to V CC when V CC exceeds V BATT + 0.03V. There is
a 60mV hysteresis around this battery switch threshold to
prevent oscillations between supplies.
While V CC is connected to V OUT the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 9.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40420 will not
acknowledge any data bytes written after the first byte
is entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
7 6 5 4 3 2 1 0
Operation
PUP1 WD1
WD0
BP
0
RWEL WEL PUP0
The device is in normal operation with V CC as long as
V CC > V TRIP1 . It switches to the battery backup mode
when V CC goes away.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V TRIP Reset Circuit
V P
V TRIP1
Adj.
V TRIP2
Adj.
V2FAIL
RESET
4.7K
1
6
2
7
X40420
14
13
9
8
Adjust
Run
SCL
SDA
μC
7
May 25, 2006
相关PDF资料 |
PDF描述 |
|---|---|
| X40420S14I-C | IC VOLT MON DUAL SUP/SW 14-SOIC |
| X40420S14I-BT1 | IC VOLT MON DUAL SUP/SW 14-SOIC |
| MAX1585ETJ+T | IC DGTL CAM PWR-SUP 5CH 32TQFN |
| X40420S14I-B | IC VOLT MON DUAL SUP/SW 14-SOIC |
| MAX1584ETJ+T | IC DGTL CAM PWR-SUP 5CH 32TQFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| X40420S14IZ-A | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.9V 3000UA 14SOIC - Rail/Tube |
| X40420S14IZ-AT1 | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.9V 3000UA 14SOIC - Tape and Reel 制造商:Intersil Corporation 功能描述:Supervisory Circuits DL VAGE CPU SUPS HI IND VTRIP1 4 6 |
| X40420S14IZ-B | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.6V 3000UA 14SOIC - Rail/Tube |
| X40420S14IZ-BT1 | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.6V 3000UA 14SOIC - Tape and Reel |
| X40420S14Z-A | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.9V 3000UA 14SOIC - Rail/Tube |
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