参数资料
| 型号： | X4285V8I-4.5A |
| 厂商： | Intersil |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 128K EE 8TSSOP |
| 标准包装： | 100 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 复位： | 高有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 4.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
X4283, X4285
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge,
Figure 14. Sequential Read Sequence
indicating it requires additional data. The device con-
tinues to output data for each acknowledge received.
The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
0000 H and the device continues to output data for each
acknowledge received. Refer to Figure 14 for the
acknowledge and data transfer sequence.
Signals from
the Master
Slave
Address
A
C
K
A
C
K
A
C
K
S
t
o
p
SDA Bus
1
Signals from
the Slave
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
X4283, X4285 Addressing
S LAVE A DDRESS B YTE
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array
– one bits of ‘0’.
– next two bits are the device address select bits S1
and S0.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
14
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
FN8121.1
May 23, 2006
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