参数资料
型号: X4643V8-2.7A
厂商: Intersil
文件页数: 2/21页
文件大小: 0K
描述: IC SUPERVISOR CPU 64K EE 8-TSSOP
标准包装: 200
类型: 简单复位/加电复位
监视电压数目: 1
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 2.92V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
X4643, X4645
PIN CONFIGURATION
8-Pin JEDEC SOIC
S 0
S 1
RESET/RESET
V SS
1
2
3
4
8
7
6
5
V CC
WP
SCL
SDA
8 Pin TSSOP
WP
V CC
S 0
S 1
1
2
3
4
8
7
6
5
SCL
SDA
V SS
RESET/RESET
PIN FUNCTION
Pin
Pin
(SOIC)
1
2
3
(TSSOP)
3
4
5
Name
S 0
S 1
RESET/RESET
Function
Device Select Input
Device Select Input
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V CC falls below the minimum V CC sense level. It
will remain active until V CC rises above the minimum V CC sense level for
250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA
remains either HIGH or LOW longer than the selectable Watchdog time out pe-
riod. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer.
RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
4
5
6
7
V SS
SDA
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open
drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) re-
starts the Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time out period results in RESET/RESET going active.
6
8
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output.
7
1
WP
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
8
2
2
V CC
Supply Voltage
FN8123.0
March 29, 2005
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