参数资料
型号: X4C105V20-3AT1
厂商: Intersil
文件页数: 6/14页
文件大小: 0K
描述: IC SUPERVISOR NOVRAM/EE 20-TSSOP
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 2.875V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
X4C105
Serial Read Operations
BYTE LOAD
COMPLETED BY
ISSUING STOP
ISSUE START
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the slave
address byte is set to one. There are three basic read
operations: current address read, random read, and
sequential read.
Current Address Read
ISSUE SLAVE
ADDRESS BYTE
ACK
RETURNED?
YES
NO
ISSUE STOP
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Upon receipt of the slave address byte with the R/W bit set to
one, the device issues an acknowledge and then transmits
HIGH VOLTAGE
CYCLE COMPLETE.
CONTINUE
COMMAND
YES
CONTINUE NORMAL
READ OR WRITE
COMMAND
NO
ISSUE STOP
the eight bits of the data byte. The master terminates the read
operation when it does not respond with an acknowledge
during the ninth clock and then issues a stop condition. Refer
to Figure 9 for the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
PROCEED
FIGURE 8. ACKNOWLEDGE POLLING SEQUENCE
Acknowledge Polling
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the stop condition is issued to indicate the end of the
master ’s byte load operation, the device initiates the internal
non volatile write cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start condition
followed by the slave address byte for a write or read
operation. If the device is still busy with the high voltage
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
Refer to the flow chart in Figure 8.
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
Random Read
A random read operation allows the master to access any
memory location in the array. Prior to issuing the slave
address byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the slave address byte, receives an
acknowledge, then issues the word address byte. After
acknowledging receipts of the word address byte, the master
immediately issues another start condition and the slave
address byte with the R/W bit set to one. This is followed by
an acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. Refer to Figure 10 for the address, acknowledge
and data transfer sequence.
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
S
T
A
R
T
SLAVE
ADDRESS
1
A
C
K
DATA
S
T
O
P
SLAVE
FIGURE 9. CURRENT ADDRESS READ SEQUENCE
6
FN8124.2
July 3, 2008
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