参数资料
| 型号： | X5001V8I-2.7 |
| 厂商： | Intersil |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 8-TSSOP |
| 标准包装： | 100 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.63V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
X5001
Watchdog Timer Register
Read Watchdog Timer Register Operation
7
0
6
0
5
0
4
WD 1
3
WD 0
2
0
1
0
0
0
If there is not a nonvolatile write in progress, the read
watchdog timer instruction returns the setting of the
watchdog timer control bits. The other bits are
Watchdog Timer Control Bits
The watchdog timer control bits, WD 0 and WD 1 ,
select the watchdog time out period. These nonvola-
tile bits are programmed with the set watchdog timer
(SWDT) instruction.
reserved and will return’0’ when read. See Figure 3.
If a nonvolatile write is in progress, the read watchdog
timer register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a separate read
watchdog timer instruction should be used to determine
the current status of the watchdog control bits.
Watchdog Control Bits
WD1 WD0
0 0
0 1
Watchdog Time Out
(Typical)
1.4 seconds
600 milliseconds
RESET Operation
The RESET (X5001) output is designed to go LOW
whenever V CC has dropped below the minimum trip
point and/or the watchdog timer has reached its pro-
1
1
0
1
200 milliseconds
disabled
grammable time out limit.
The RESET output is an open drain output and
requires a pull-up resistor.
Write Watchdog Register Operation
Changing the watchdog timer register is a two step
process. First, the change must be enabled by setting
the watchdog change latch (see below). This instruc-
tion is followed by the set watchdog timer (SWDT)
instruction, which includes the data to be written (Fig-
ure 5). Data bits 3 and 4 contain the watchdog settings
and data bits 0, 1, 2, 5, 6 and 7 must be “0”.
Watchdog Change Latch
The watchdog change latch must be SET before a
Write watchdog timer operation is initiated. The
Enable Watchdog Change (EWDC) instruction will set
the latch and the Disable Watchdog Change (DWDC)
instruction will reset the latch (Figure 6). This latch is
automatically reset upon a power-up condition and
after the completion of a valid nonvolatile write cycle.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The watchdog change latch is reset.
– The RESET signal is active for t PURST .
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A EWDC instruction must be issued to enable a
change to the watchdog timeout setting.
– CS must come HIGH at the proper clock count in
order to implement the requested changes to the
watchdog timeout setting.
Table 1. Instruction Set Definition
Instruction Format
0000 0110
0000 0100
0000 0001
0000 0101
Instruction Name and Operation
EWDC: Enable Watchdog Change Operation
DWDC: Disable Watchdog Change Operation
SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD 1 ) (WD 0 )000
See Watchdog Timer Settings and Figure 7.
RWDT: Read Watchdog Timer Control Bits
Note:
Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
8
FN8125.1
May 30, 2006
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| X5001V8I-4.5A | 功能描述:IC SUPERVISOR CPU 8-TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:推挽式，图腾柱 复位:低有效 复位超时:最小 145 ms 电压 - 阀值:2.64V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-WQFN 裸露焊盘 供应商设备封装:16-TQFN-EP（4x4） 包装:带卷 (TR) |
| X5001V8IZ-2.7 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor |
| X5001V8IZ-2.7A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor |
| X5001V8Z-2.7 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor |
| X5001V8Z-2.7A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CPU Supervisor |
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