参数资料
型号: X5163PI-4.5A
厂商: Intersil
文件页数: 4/21页
文件大小: 0K
描述: IC SUPERVISOR CPU 16K EE 8-DIP
标准包装: 50
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 4.63V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
X5163, X5165
Block Diagram
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
SI
SO
Data
Register
Status
Register
RESET/RESET
SCK
CS/WDI
Command
Decode &
Control
Logic
4K Bits
4K Bits
Reset &
Watchdog
Timebase
X5163 = RESET
X5165 = RESET
V CC Threshold
Reset Logic
8K Bits
V CC
Pin Description
PIN
V TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
(SOIC/PDIP)
1
PIN TSSOP
1
NAME
CS/WDI
FUNCTION
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH
to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW
transition within the watchdog time out period results in RESET/RESET going active.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
4
5
7
8
V SS
SI
Ground
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
7
13
RESET/
RESET
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above
the minimum V CC sense level for 200ms. RESET/RESET goes active if the Watchdog Timer is
enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out
period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power-
up at 1V and remains active for 200ms after the power supply stabilizes.
8
14
3-5,10-12
4
V CC
NC
Supply Voltage
No internal connections
FN8128.3
June 1, 2006
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