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参数资料
| 型号： | X5645S14 |
| 厂商： | Intersil |
| 文件页数： | 2/19页 |
| 文件大小： | 0K |
| 描述： | IC CPU SUPRV 64K EE RST HI SO14 |
| 标准包装： | 100 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 4.38V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 管件 |
X5643, X5645
PIN CONFIGURATION
14-Lead SOIC
8-Lead PDIP
NC
1
14
NC
CS/WDI
1
8
V CC
CS/WDI
2
13
V CC
SO
WP
2
3
X5643/45
7
6
RESET/RESET
SCK
CS/WDI
SO
WP
3 12
4 X5643/45 11
5 10
V CC
RESET/RESET
SCK
V SS
4
5
SI
V SS
6
9
SI
Pin
Pin
Pin
NC
7
8
NC
PDIP
1
SOIC
2&3
TSSOP
2
Name
CS/WDI
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power-up, a
HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog
timer. The absence of a HIGH to LOW transition within the watchdog time out
period results in RESET/RESET going active.
2
4
3
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
5
9
13
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
10
14
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
3
5
7
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
4
8
7
6
12 & 13
11
8
19
18
V SS
V CC
RESET/
Ground
Supply Voltage
Reset Output . RESET/RESET is an active LOW/HIGH, open drain output
RESET
which goes active whenever V CC falls below the minimum V CC sense level. It
will remain active until V CC rises above the minimum V CC sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out pe-
riod. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power-up at about 1V and remains active for 200ms after the power
supply stabilizes.
1, 7, 8,
14
1, 4-6,
9-12,
NC
No internal connections
15-17, 20
2
FN8135.1
July 18, 2005
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相关代理商/技术参数 |
参数描述 |
|---|---|
| X5645S14-1.8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X5645S14-2.7 | 功能描述:IC CPU SUPRV 64K EE RST HI SO14 RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:低有效 复位超时:标准传输延迟为 60 µs 电压 - 阀值:3V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:Digi-Reel® 其它名称:LM8364BALMF30DKR |
| X5645S14-2.7A | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
| X5645S14-4.5A | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
| X5645S14I | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
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