参数资料
型号: X9401WV24Z-2.7
厂商: Intersil
文件页数: 14/18页
文件大小: 0K
描述: IC XDCP QUAD 64-TAP 10K 24-TSSOP
标准包装: 62
系列: XDCP™
接片: 64
电阻(欧姆): 10k
电路数: 4
温度系数: 标准值 ±300 ppm/°C
存储器类型: 非易失
接口: 6 线 SPI(芯片选择,设备位址)
电源电压: 2.7 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
5
FN8190.4
October 13, 2009
or directly between the host and the Wiper Counter Register.
These instructions are:
Read Wiper Counter Register: read the current wiper
position of the selected pot,
Write Wiper Counter Register: change current wiper
position of the selected pot,
Read Data Register: read the contents of the selected
data register;
Write Data Register: write a new value to the selected data
register.
Read Status: This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The sequence of these operations is shown in Figure 4 and
Figure 5.
The final command is Increment/Decrement. It is different
from the other commands, because it’s length is
indeterminate. Once the command is issued, the master can
clock the selected wiper up and/or down in one resistor
segment steps; thereby, providing a fine tuning capability to
the host. For each SCK clock pulse (tHIGH) while SI is HIGH,
the selected wiper will move one resistor segment towards
the VH/RH terminal. Similarly, for each SCK clock pulse
while SI is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown in
Figure 6 and Figure 7.
Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCL
UP/DN
VH/RH
VL/RL
VW/RW
IF WCR = 00[H] THEN VW/RW = VL/RL
IF WCR = 3F[H] THEN VW/RW = VH/RH
8
6
C
O
U
N
T
E
R
D
E
C
O
D
E
(WCR)
(ONE OF FOUR ARRAYS)
X9401
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