参数资料
| 型号： | X9455UV24-2.7 |
| 厂商： | Intersil |
| 文件页数： | 4/19页 |
| 文件大小： | 0K |
| 描述： | IC DCP DUAL 50K 256TAP 24-TSSOP |
| 标准包装： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 2 |
| 温度系数： | 标准值 ±300 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 9 线串行（芯片选择，设备位址，动触点位址） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
12
FN8202.1
July 28, 2006
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to figure 4.). This byte includes
three parts:
The four MSBs (SA7-SA4) are the Device Type Identifier,
which must always be set to 0101 in order to select the
X9455.
The next three bits (SA3-SA1) are the Device Address bits
(AS2-AS0). To access any part of the X9455’s memory,
the value of bits AS2, AS1, and AS0 must correspond to
the logic levels at pins A2, A1, and A0 respectively.
The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being addressed.
When the R/W bit is “1”, then a Read operation is
selected. A “0” selects a Write operation
.
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X9455
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, any Read or Write
command is ignored by the X9455. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X9455’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. (Refer to figure 5.)
2-Wire Serial Interface Operation
X9455 Digital Potentiometer Register Organization
Refer to the Functional Diagram on page 1. There are 2
Digital Potentiometers, referred to as DCP0, and DCP1.
Each potentiometer has two volatile Wiper Control Registers
(WCRs). Each wiper has four non-volatile registers to store
wiper position or general data. See Table 2 for register
numbering.
SA6
SA7
SA5
SA3
SA2
SA1
SA0
Device Type
Identifier
Read or
SA4
SLAVE ADDRESS
BIT(S)
DESCRIPTION
SA7-SA4
Device Type Identifier
SA3-SA1
Device Address
SA0
Read or Write Operation Select
R/W
01
0
1
Address
Device
AS0
AS1
AS2
Write
FIGURE 4. SLAVE ADDRESS (SA) FORMAT
ACK returned?
Issue Slave Address
Byte (Read or Write)
Byte load completed by issuing
STOP. Enter ACK Polling
Issue STOP
Issue START
NO
YES
NO
Continue normal Read or Write
command sequence
PROCEED
YES
complete. Continue command
sequence.
High Voltage
Issue STOP
FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE
X9455
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