参数资料
| 型号： | X95820WV14I-2.7T1 |
| 厂商： | Intersil |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC XDCP DUAL 256TAP 10K 14-TSSOP |
| 标准包装： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 电阻（欧姆）： | 10k |
| 电路数： | 2 |
| 温度系数： | 标准值 ±45 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
4
FN8212.2
July 18, 2006
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
ICC1
VCC Supply Current
(Volatile write/read)
fSCL = 400kHz;SDA = Open; (for I
2C,
Active, Read and Volatile Write States only)
1mA
ICC2
VCC Supply Current
(nonvolatile write)
fSCL = 400kHz; SDA = Open; (for I
2C,
Active, Nonvolatile Write State only)
3mA
ISB
VCC Current (standby)
VCC = +5.5V, I
2C Interface in Standby State
5
A
VCC = +3.6V, I
2C Interface in Standby State
2
A
ILkgDig
Leakage Current, at Pins A0,
A1, A2, SDA, SCL, and WP
Pins
Voltage at pin from GND to VCC
-10
10
A
tDCP
(Note 15)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1s
Vpor
Power-on Recall Voltage
Minimum VCC at which memory recall occurs
1.8
2.6
V
VccRamp
VCC Ramp Rate
0.2
V/ms
Power-up Delay
VCC above Vpor, to DCP Initial Value Register recall
completed, and
I2C Interface in standby state
3ms
EEPROM SPECS
EEPROM Endurance
150,000
Cycles
EEPROM Retention
Temperature
≤ 75°C
50
Years
SERIAL INTERFACE SPECS
VIL
WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
-0.3
0.3*Vcc
V
VIH
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
0.7*Vcc
Vcc+0.3
V
Hysterisis
(Note 15)
SDA and SCL input buffer
hysterisis
0.05*
Vcc
V
VOL
(Note 15)
SDA Output Buffer LOW
Voltage, Sinking 4mA
00.4
V
Cpin
(Note 15)
WP, A2, A1, A0, SDA, and
SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN
(Note 15)
Pulse Width Suppression
Time at SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
tAA
(Note 15)
SCL Falling Edge to SDA
Output Data Valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window.
900
ns
tBUF
(Note 15)
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VCC during a STOP condition,
to SDA crossing 70% of VCC during the following
START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup
Time
SCL rising edge to SDA falling edge. Both crossing
70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC.
600
ns
X95820
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