参数资料
型号: XA3S250E-4TQG144I
厂商: Xilinx Inc
文件页数: 21/37页
文件大小: 0K
描述: IC FPGA SPARTAN-3E 250K 144-TQFP
标准包装: 60
系列: Spartan®-3E XA
LAB/CLB数: 612
逻辑元件/单元数: 5508
RAM 位总计: 221184
输入/输出数: 108
门数: 250000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
DS635 (v2.0) September 9, 2009
Product Specification
28
R
Miscellaneous DCM Timing
Table 31: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Units
Phase Shifting Range
MAX_STEPS(2)
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the clock
effective clock period.
CLKIN < 60 MHz
±[INTEGER(10
(TCLKIN – 3 ns))]
steps
CLKIN > 60 MHz
±[INTEGER(15
(TCLKIN – 3 ns))]
steps
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
±[MAX_STEPS
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase shifting
±[MAX_STEPS
DCM_DELAY_STEP_MAX]
ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 6 and Table 30.
2.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT
attribute is set to 0.
3.
The DCM_DELAY_STEP values are provided at the bottom of Table 27.
Table 32: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN(1)
Minimum duration of a RST pulse width
3
-CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
seconds
N/A
seconds
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA
configuration successfully completed (DONE pin goes
High) and clocks applied to DCM DLL
N/A
minutes
N/A
minutes
Notes:
1.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2.
This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs.
3.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
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XA3S250E-4VQG100I 功能描述:IC FPGA SPARTAN-3E 250K 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:Spartan®-3E XA 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA(27x27)
XA3S250E-4VQG100Q 功能描述:IC FPGA SPARTAN-3E 250K 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:Spartan®-3E XA 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA(27x27)
XA3S400-4FGG456I 功能描述:IC FPGA SPARTAN-3 400K 456-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:Spartan®-3 XA 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA(27x27)
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