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参数资料
| 型号： | XC1765ELVO8I |
| 厂商： | Xilinx Inc |
| 文件页数： | 1/13页 |
| 文件大小： | 0K |
| 描述： | IC PROM SER I-TEMP 3.3V 8-SOIC |
| 产品变化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 Product Discontinuation 28/Jul/2010 |
| 标准包装： | 98 |
| 可编程类型： | OTP |
| 存储容量： | 65kb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-TSOP |
| 包装： | 管件 |
DS027 (v3.5) June 25, 2008
Product Specification
1
Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Features
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGAs
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration
Low-power CMOS floating-gate process
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
Available in compact plastic packages: 8-pin SOIC, 8-
pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-
pin PLCC or 44-pin VQFP
Programming support by leading programmer
manufacturers
Design support using the Xilinx Alliance and
Foundation software packages
Guaranteed 20 year life data retention
Lead-free (Pb-free) packaging available
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See Figure 1 for a
simplified block diagram.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or
Foundation software compiles the FPGA design file into a
standard Hex format, which is then transferred to most
commercial PROM programmers.
<
B
L
XC1700E, XC1700EL, and XC1700L
Series Configuration PROMs
DS027 (v3.5) June 25, 2008
8
Product Specification
R
X-Ref Target - Figure 1
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC
VPP
GND
DS027_01_021500
TC
OE
RESET/
OE/
RESET
or
CEO
Product Obsolete or Under Obsolescence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC1765ELVOG8C | 功能描述:IC 3V SER CFG PROM 65K 8-SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:- 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
| XC1765EPC20C | 功能描述:IC PROM SER C-TEMP 3.3V 20-PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:- 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
| XC1765EPC20I | 功能描述:IC PROM SER I-TEMP 3.3V 20-PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:- 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
| XC1765EPC2OC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Configuration EPROM |
| XC1765EPC2OI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Configuration EPROM |
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