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参数资料
| 型号： | XC17S30XLVO8I |
| 厂商： | Xilinx Inc |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC 3V PROM SER 300K 8-SOIC |
| 产品变化通告： | Product Discontinuation 28/Jul/2010 |
| 标准包装： | 98 |
| 可编程类型： | OTP |
| 存储容量： | 300kb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-TSOP |
| 包装： | 管件 |
Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL)
DS030 (v1.12) June 20, 2008
Product Specification
3
R
Controlling PROMs
Connecting the Spartan device with the PROM:
The DATA output of the PROM drives the DIN input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a VCC glitch. Other
methods—such as driving RESET/OE from LDC or
system reset—assume that the PROM internal power-
on-reset is always in step with the FPGAs internal
power-on-reset, which is not a safe assumption.
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
High during user operation. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
Spartan FPGA PROM has been designed for compatibility
with the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is
Low. Data is read from the PROM sequentially on a single
data line. Synchronization is provided by the rising edge
of the temporary signal CCLK, which is generated during
configuration.
Master Serial mode provides a simple configuration
interface (Figure 1, page 4). Only a serial data line and two
control lines are required to configure the Spartan device.
Data from the PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan family takes care of this automatically with an on-
chip default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE pin is held Low, the address
counters are left unchanged after configuration is complete.
Therefore, to reprogram the FPGA with another program,
the DONE line is pulled Low and configuration begins at the
last value of the address counters.
This method fails if a user applies RESET during the
Spartan device configuration process. The Spartan device
aborts the configuration and then restarts a new
configuration, as intended, but the PROM does not reset its
address counter, since it never saw a High level on its OE
input. The new configuration, therefore, reads the remaining
data in the PROM and interprets it as preamble, length
count etc. Since the Spartan device is the Master, it issues
the necessary number of CCLK pulses, up to 16 million
(224) and DONE goes High. However, the Spartan device
configuration will be completely wrong, with potential
contentions inside the Spartan device and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming the Spartan Family
PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Product Obsolete or Under Obsolescence
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| XC17S30XL-VO8I | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XC17S30XLVOG8C | 功能描述:IC PROM SERIAL 3.3V 300K 8-SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:- 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
| XC17S30XLVOG8I | 功能描述:IC PROM SERIAL 3.3V 300K 8-SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:- 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
| XC17S40 | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XC17S40PD8C | 功能描述:IC PROM PROG C-TEMP 5V 8-DIP RoHS:否 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:- 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
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