参数资料
型号: XC17V02PC20C
厂商: Xilinx Inc
文件页数: 5/15页
文件大小: 0K
描述: IC PROM SER 2MBIT 3.3V 20-PLCC
产品变化通告: Product Discontinuation Notice 14/May/2007
标准包装: 46
可编程类型: OTP
存储容量: 2Mb
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 20-LCC(J 形引线)
供应商设备封装: 20-PLCC
包装: 管件
XC17V00 Series Configuration PROMs
DS073 (v2.0) April 7, 2014
Product Specification
13
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
AC Characteristics over Operating Condition When Cascading
Ordering Information
X-Ref Target - Figure 6
Symbol
Description
Min
Max
Units
TCDF
CLK to data float delay(2,3)
–50
ns
TOCK
CLK to CEO delay(3)
–30
ns
TOCE
CE to CEO delay(3)
–35
ns
TOOE
RESET/OE to CEO delay(3)
–30
ns
Notes:
1.
AC test load = 50 pF.
2.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3.
Guaranteed by design, not tested.
4.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
CLK
DATA
CE
CEO
First Bit
Last Bit
TCDF
DS026_07_102005
RESET/OE
TOCK
TOOE
TOCE
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing of the First Bit and Last Bit for one PROM with respect to signals involved in a cascaded situation.
The diagram does not show timing of data as one PROM transfers control to the next PROM. The shown timing information must
be applied appropriately to each PROM in a cascaded situation to understand the timing of data during the transfer of control
from one PROM to the next.
XC17V16 PC44 C
Operating Range/Processing
C = Commercial (TA = 0° to +70°C)
I = Industrial (TA = –40° to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
Device Number
XC17V16
XC17V04
XC17V01
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