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参数资料
| 型号： | XC17V08PC44I |
| 厂商： | Xilinx Inc |
| 文件页数： | 15/15页 |
| 文件大小： | 0K |
| 描述： | IC PROM SER I-TEMP 3.3V 44-PLCC |
| 产品变化通告： | Product Discontinuation Notice 14/May/2007 |
| 标准包装： | 26 |
| 可编程类型： | OTP |
| 存储容量： | 8Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
XC17V00 Series Configuration PROMs
DS073 (v2.0) April 7, 2014
Product Specification
9
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Notes:
1.
Specific part number and package combinations have been discontinued. Refer to XCN07010.
X-Ref Target - Figure 3
Figure 3: (a) Master Serial Mode (b) SelectMAP Mode
(dotted lines indicate optional connection)
PROGRAM
DIN
CCLK
INIT
DONE
First
PROM
DATA
CEO
BUSYBUSY
CLK
CE
OPTIONAL
Slave FPGAs
with identical
configurations
FPGA
(Low Resets the Address Pointer)
VCC
Vpp
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
OE/RESET
DOUT
Modes(1)
BUSYBUSY
SelectMAP Mode, XC17V16 and XC17V08(1) only.
4.7K
VCC
Vpp
VCC
(2)
Master Serial Mode
DS073_03_102708
(1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
Cascaded
PROM
DATA
CLK
CE
OE/RESET
PROGRAM
BUSY
CS
WRITE
INIT
D[0:7]
CCLK
DONE
CLK
D[0:7]
CE
OE/RESET
First
PROM
Second
PROM
Modes(3)
3.3V
External
Osc(4)
CEO
4.7K
(2)
VCC
Vpp
VCC
1K
I/O(1)
8
I/O(1)
1K
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(4) External oscillator required for FPGA slave SelectMAP modes.
CLK
D[0:7]
CE
OE/RESET
CEO
VCC
Vpp
FPGA
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