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参数资料
型号： XC2S100E-6PQG208C
厂商： Xilinx Inc
文件页数： 27/108页
文件大小： 0K
描述： IC FPGA 1.8V 600 CLB'S 208-PQFP
产品变化通告： FPGA Family Discontinuation 18/Apr/2011
标准包装： 24
系列： Spartan®-IIE
LAB/CLB数： 600
逻辑元件/单元数： 2700
RAM 位总计： 40960
输入/输出数： 146
门数： 100000
电源电压： 1.71 V ~ 1.89 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 208-BFQFP
供应商设备封装： 208-PQFP（28x28）
DS077-2 (v3.0) August 9, 2013
www.xilinx.com
25
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Slave Serial Mode
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing the FPGA to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration. Figure 19 shows connections for
a Master Serial FPGA configuring a Slave Serial FPGA
from a PROM. A Spartan-IIE device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2). The weak pull-ups on the mode pins
make slave serial the default mode if the pins are left uncon-
nected.
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally gener-
ated CCLK.
Timing for Slave Serial mode is shown in Figure 24,
page 49.
Daisy Chain
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. After an FPGA is
configured, data for the next device is sent to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
Note that DOUT changes on the falling edge of CCLK for
some Xilinx families but mixed daisy chains are allowed.
Configuration must be delayed until INIT pins of all
daisy-chained FPGAs are High. For more information, see
Start-up, page 23.
The maximum amount of data that can be sent to the DOUT
pin for a serial daisy chain is 220-1 (1,048,575) 32-bit words,
or 33,554,400 bits, which is approximately 8 XC2S600E bit-
streams. The configuration bitstream of downstream
devices is limited to this size.
Figure 18: Loading Serial Mode Configuration Data
No
Yes
End of
Configuration
Data File?
After INIT
Goes High
User Load One
Configuration
Bit on Next
CCLK Rising Edge
To CRC Check
DS001_14_032300
Notes:
1.
If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330
Ω resistor.
Figure 19: Master/Slave Serial Configuration Circuit Diagram
Spartan-IIE
(Master Serial)
Xilinx
PROM
PROGRAM
M2
M0 M1
DOUT
CCLK
CLK
3.3V
DATA
CE
CEO
RESET/OE
DIN
INIT
DONE
PROGRAM
3.3 K
DS077-2_04_061708
GND
VCC
3.3V
VCCO
VCCINT
1.8V
3.3V
1.8V
Spartan-IIE
(Slave)
DONE
INIT
PROGRAM
CCLK
DIN
DOUT
M2
M0 M1
GND
VCCO
VCCINT
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XC2S100E-6PQG208I 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA
XC2S100E-6TQ144C 功能描述:IC FPGA 1.8V 600 CLB'S 144-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27）
XC2S100E-6TQ144C0776 制造商:Xilinx 功能描述:
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XC2S100E-6TQG144C 功能描述:IC FPGA 1.8V 600 CLB'S 144-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27）
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