- 您现在的位置：买卖IC网 > PDF目录19312 > XC2S15-5VQG100C (Xilinx Inc)IC SPARTAN-II FPGA 15K 100-VQFP PDF资料下载
参数资料
| 型号： | XC2S15-5VQG100C |
| 厂商： | Xilinx Inc |
| 文件页数： | 5/99页 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-II FPGA 15K 100-VQFP |
| 标准包装： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB数： | 96 |
| 逻辑元件/单元数： | 432 |
| RAM 位总计： | 16384 |
| 输入/输出数： | 60 |
| 门数： | 15000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
| 产品目录页面： | 599 (CN2011-ZH PDF) |
| 其它名称： | 122-1309 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
13
R
Clock Distribution
The Spartan-II family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the
general purpose routing. Global clock pins do not have the
option for internal, weak pull-up resistors.
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully
digital Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the
distributed clock, and automatically adjusts a clock delay
element. Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. It has six outputs.
The DLL also operates as a clock mirror. By driving the
output from a DLL off-chip and then back on again, the DLL
can be used to deskew a board level clock among multiple
Spartan-II devices.
In order to guarantee that the system clock is operating
correctly prior to the FPGA starting up after configuration,
the DLL can delay the completion of the configuration
process until after it has achieved lock.
Boundary Scan
Spartan-II devices support all the mandatory boundary-
scan instructions specified in the IEEE standard 1149.1. A
Test Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP also supports two USERCODE
instructions and internal scan chains.
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO
for Bank 2 must be 3.3V. Otherwise, TDO switches
rail-to-rail between ground and VCCO. TDI, TMS, and TCK
have a default internal weak pull-up resistor, and TDO has
no default resistor. Bitstream options allow setting any of
the four TAP pins to have an internal pull-up, pull-down, or
neither.
Figure 7: BUFT Connections to Dedicated Horizontal Bus Lines
CLB
3-State
Lines
DS001_07_090600
Figure 8: Global Clock Distribution Network
Global Clock
Spine
Global Clock
Column
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
Global
Clock Rows
DS001_08_060100
相关PDF资料 |
PDF描述 |
|---|---|
| EEM12DSXN | CONN EDGECARD 24POS DIP .156 SLD |
| RSA43DRMH | CONN EDGECARD 86POS .125 SQ WW |
| TACL335M004H | CAP TANT 3.3UF 4V 20% 0603 |
| KA79L05AZBU | IC REG LDO -5V .1A TO-92 |
| EEM12DSXH | CONN EDGECARD 24POS DIP .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S15-5VQG100I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 15K GATES 432 CELLS 263MHZ 2.5V 100VTQFP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S15-6CS144C | 功能描述:IC FPGA 2.5V C-TEMP 144-CSBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-II 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC2S15-6CS144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6CSG144C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6CSG144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
发布紧急采购，3分钟左右您将得到回复。