参数资料
| 型号： | XC2S15-6CS144C |
| 厂商： | Xilinx Inc |
| 文件页数： | 59/99页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V C-TEMP 144-CSBGA |
| 标准包装： | 198 |
| 系列： | Spartan®-II |
| LAB/CLB数： | 96 |
| 逻辑元件/单元数： | 432 |
| RAM 位总计： | 16384 |
| 输入/输出数： | 86 |
| 门数： | 15000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 144-TFBGA，CSPBGA |
| 供应商设备封装： | 144-LCSBGA（12x12） |
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Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
62
R
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of
the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark
timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were
determined through statistical measurement at the package
pins using a clock mirror configuration and matched drivers.
Figure 52, page 63, provides definitions for various
parameters in the table below.
Symbol
Description
Speed Grade
Units
-6
-5
Min
Max
Min
Max
FCLKINHF
Input clock frequency (CLKDLLHF)
60
200
60
180
MHz
FCLKINLF
Input clock frequency (CLKDLL)
25
100
25
90
MHz
TDLLPWHF
Input clock pulse width (CLKDLLHF)
2.0
-
2.4
-
ns
TDLLPWLF
Input clock pulse width (CLKDLL)
2.5
-
3.0
-
ns
Symbol
Description
F
CLKIN
CLKDLLHF
CLKDLL
Units
Min
Max
Min
Max
TIPTOL
Input clock period tolerance
-
1.0
-
1.0
ns
TIJITCC
Input clock jitter tolerance (cycle-to-cycle)
-
±150
-
±300
ps
TLOCK
Time required for DLL to acquire lock
> 60 MHz
-
20
-
20
μs
50-60 MHz
-
25
μs
40-50 MHz
-
50
μs
30-40 MHz
-
90
μs
25-30 MHz
-
120
μs
TOJITCC
Output jitter (cycle-to-cycle) for any DLL clock output(1)
-
±60
-
±60
ps
TPHIO
Phase offset between CLKIN and CLKO(2)
-
±100
-
±100
ps
TPHOO
Phase offset between clock outputs on the DLL(3)
-
±140
-
±140
ps
TPHIOM
Maximum phase difference between CLKIN and CLKO(4)
-
±160
-
±160
ps
TPHOOM
Maximum phase difference between clock outputs on the DLL(5)
-
±200
-
±200
ps
Notes:
1.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
3.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5.
Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S15-6CS144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6CSG144C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6CSG144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6FG256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6FG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
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