参数资料
| 型号： | XC2S30-6CS144C |
| 厂商： | Xilinx Inc |
| 文件页数： | 10/99页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V C-TEMP 144-CSBGA |
| 标准包装： | 198 |
| 系列： | Spartan®-II |
| LAB/CLB数： | 216 |
| 逻辑元件/单元数： | 972 |
| RAM 位总计： | 24576 |
| 输入/输出数： | 92 |
| 门数： | 30000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 144-TFBGA，CSPBGA |
| 供应商设备封装： | 144-LCSBGA（12x12） |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
18
R
Signals
There are two kinds of pins that are used to configure
Spartan-II devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an
input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
For a more detailed description than that given below, see
"Pinout Tables" in Module 4 and XAPP176, Spartan-II
FPGA Series Configuration and Readback.
The Process
The sequence of steps necessary to configure Spartan-II
devices are shown in Figure 11. The overall flow can be
divided into three different phases.
Initiating Configuration
Configuration memory clear
Loading data frames
Start-up
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
Initiating Configuration
There are two different ways to initiate the configuration
process: applying power to the device or asserting the
PROGRAM input.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
shown in Figure 12, page 19. Before configuration can
begin, VCCO Bank 2 must be greater than 1.0V.
Furthermore, all VCCINT power pins must be connected to a
2.5V supply. For more information on delaying
configuration, see "Clearing Configuration Memory,"
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process
by driving DONE Low, then enters the memory-clearing
phase.
Figure 11: Configuration Flow Diagram
FPGA Drives
INIT Low
Abort Start-up
User Holding
INIT
Low?
User Holding
PROGRAM
Low?
FPGA
Drives INIT
and DONE Low
Load
Configuration
Data Frames
User Operation
Configuration
at Power-up
DS001_11_111501
No
CRC
Correct?
Yes
FPGA
Samples
Mode Pins
Delay
Configuration
Delay
Configuration
Clear
Configuration
Memory
User Pulls
PROGRAM
Low
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
Yes
No
Yes
No
Yes
Configuration During
User Operation
VCCO
AND
VCCINT
High?
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相关代理商/技术参数 |
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| XC2S30-6CS144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S30-6CSG144C | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 144CSBGA - Trays |
| XC2S30-6CSG144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S30-6FG256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S30-6FG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
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