参数资料
型号: XC2S50-5PQ208I
厂商: Xilinx Inc
文件页数: 67/99页
文件大小: 0K
描述: IC FPGA 2.5V I-TEMP 208-PQFP
标准包装: 24
系列: Spartan®-II
LAB/CLB数: 384
逻辑元件/单元数: 1728
RAM 位总计: 32768
输入/输出数: 140
门数: 50000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
7
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trademarks are the property of their respective owners.
Architectural Description
Spartan-II FPGA Array
The Spartan-II field-programmable gate array, shown in
Figure 2, is composed of five major configurable elements:
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
As can be seen in Figure 2, the CLBs form the central logic
structure with easy access to all support and routing
structures. The IOBs are located around all the logic and
memory elements for easy and quick routing of signals on
and off the chip.
Values stored in static memory cells control all the
configurable logic elements and interconnect resources.
These values load into the memory cells on power-up, and
can reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the
following sections.
Input/Output Block
The Spartan-II FPGA IOB, as seen in Figure 2, features
inputs and outputs that support a wide variety of I/O
signaling standards. These high-speed inputs and outputs
are capable of supporting various state of the art memory
and bus interfaces. Table 3 lists several of the standards
which are supported along with the required reference,
output and termination voltages needed to meet the
standard.
50
Spartan-II FPGA Family:
Functional Description
DS001-2 (v2.8) June 13, 2008
Product Specification
R
Figure 2: Spartan-II FPGA Input/Output Block (IOB)
Package Pin
Package
Pin
Package Pin
D
CK
EC
SR
Q
D
CK
EC
SR
Q
D
CK
EC
SR
Q
Programmable
Bias &
ESD Network
VCCO
I/O
I/O, VREF
Internal
Reference
To Next I/O
To Other
External VREF Inputs
of Bank
Programmable
Input Buffer
Programmable
Output Buffer
Programmable
Delay
VCC
OE
SR
O
OCE
I
ICE
IQ
CLK
TCE
T
DS001_02_090600
TFF
OFF
IFF
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XC2S50-5PQG208I 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 208PQFP - Trays
XC2S50-5TQ144C 功能描述:IC FPGA 2.5V 384 CLB'S 144-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:Spartan®-II 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA(27x27)
XC2S50-5TQ144C-ES 制造商:Xilinx 功能描述:2S50-5TQ144C-ES
XC2S50-5TQ144I 功能描述:IC FPGA 2.5V I-TEMP 144-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:Spartan®-II 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA(27x27)