参数资料
型号: XC3090A-7PC84C
厂商: Xilinx Inc
文件页数: 26/76页
文件大小: 0K
描述: IC LOGIC CL ARRAY 9000GAT 84PLCC
产品变化通告: Product Discontinuation 27/Apr/2010
标准包装: 1
系列: XC3000A/L
LAB/CLB数: 320
RAM 位总计: 64160
输入/输出数: 70
门数: 6000
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC
其它名称: 122-1034
XC3090A-7PC84C-ND
R
XC3000 Series Field Programmable Gate Arrays
7-34
November 9, 1998 (Version 3.1)
General XC3000 Series Switching Characteristics
Notes:
1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a
non-monotonically rising VCC may require a >1-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L).
4 TMRW
2 TMR
3 TRM
5 TPGW
6 TPGI
Clear State
Configuration State
User State
Note 3
VCCPD
X5387
RESET
M0/M1/M2
DONE/PROG
INIT
(Output)
PWRDWN
VCC (Valid)
Description
Symbol
Min
Max
Units
RESET (2)
M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
2
3
4
TMR
TRM
TMRW
1
4.5
6
s
DONE/PROG
Width (Low) required for Re-config.
INIT response after D/P is pulled Low
5
6
TPGW
TPGI
6
7
s
PWRDWN (3)
Power Down VCC
VCCPD
2.3
V
Product Obsolete or Under Obsolescence
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