参数资料
型号: XC3120A-3PC68C
厂商: Xilinx Inc
文件页数: 17/76页
文件大小: 0K
描述: IC LOGIC CL ARRAY 2000GAT 68PLCC
产品变化通告: XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
标准包装: 18
系列: XC3000A/L
LAB/CLB数: 64
RAM 位总计: 14779
输入/输出数: 58
门数: 1500
电源电压: 4.25 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC
其它名称: 122-1037
R
XC3000 Series Field Programmable Gate Arrays
7-26
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
TDSCK
2
TCKDS
n
n + 1
n + 2
n – 3
n – 2
n – 1
n
X3223
Description
Symbol
Min
Max
Units
CCLK
Data In setup
1
TDSCK
60
ns
Data In hold
2
CKDS
0ns
Product Obsolete or Under Obsolescence
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