参数资料
| 型号： | XC3S1600E-4FGG400I |
| 厂商： | Xilinx Inc |
| 文件页数： | 182/227页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3E 1600K 400FBGA |
| 标准包装： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB数： | 3688 |
| 逻辑元件/单元数： | 33192 |
| RAM 位总计： | 663552 |
| 输入/输出数： | 304 |
| 门数： | 1600000 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 400-BGA |
| 供应商设备封装： | 400-FBGA（21x21） |
| 配用： | HW-XA3S1600E-UNI-G-ND - KIT DEVELOPMENT AUTOMOTIVE ECU |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
58
Clocking Infrastructure
For additional information, refer to the “Using Global Clock
Resources” chapter in UG331.
The Spartan-3E clocking infrastructure, shown in Figure 45,
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals
throughout the FPGA. The infrastructure also includes the
clock inputs and BUFGMUX clock buffers/multiplexers. The
Xilinx Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Clock Inputs
Clock pins accept external clock signals and connect
directly to DCMs and BUFGMUX elements. Each
Spartan-3E FPGA has:
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
Clock inputs optionally connect directly to DCMs using
show the clock inputs that best feed a specific DCM within a
given Spartan-3E part number. Different Spartan-3E FPGA
densities have different numbers of DCMs. The
XC3S1200E and XC3S1600E are the only two densities
with the left- and right-edge DCMs.
Each clock input is also optionally a user-I/O pin and
connects to internal interconnect. Some clock pad pins are
input-only pins as indicated in Module 4, Pinout
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a
multiplexer to switch between two unrelated, possibly
asynchronous clock signals (BUFGMUX).
Each BUFGMUX element, shown in Figure 46, is a 2-to-1
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 40. The switching from one clock to the
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock. The two clock inputs
can be asynchronous with regard to each other, and the S
input can change at any time, except for a short setup time
prior to the rising edge of the presently selected clock (I0 or
I1). This setup time is specified as TGSI in Table 101,
page 137. Violating this setup time requirement possibly
results in an undefined runt pulse output.
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in Figure 46. As shown in Figure 45, there are 24
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly
global and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in Figure 46. For
example, the input on I0 of one BUFGMUX is also a shared
input to I1 of the adjacent BUFGMUX.
The clock switch matrix for the left- and right-edge
BUFGMUX elements receive signals from any of the three
following sources: an LHCLK or RHCLK pin as appropriate,
a Double-Line interconnect, or a DCM in the XC3S1200E
and XC3S1600E devices.
Table 40: BUFGMUX Select Mechanism
S Input
O Output
0
I0 Input
1
I1 Input
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| XC2V250-5CSG144C | IC FPGA VIRTEX-II 250K 144-CSBGA |
| XC2V250-4CSG144I | IC FPGA VIRTEX-II 250K 144-CSBGA |
| XC6SLX45T-N3FGG484I | IC FPGA SPARTAN-6 484FBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC3S1600E-4FGG484C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 1.6M GATES 33192 CELLS 572MHZ 90NM 1.2V 484F - Trays 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 1600K GATES 484FBGA |
| XC3S1600E-4FGG484I | 功能描述:IC FPGA SPARTAN-3E 1600K 484FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-3E 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC3S1600E-4FT256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1600E-4FT256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1600E-4FTG256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-3E FPGA Family |
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