Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
56
Revision History
Date
Version No.
Description
04/11/2003
1.0
Initial Xilinx release
05/19/2003
1.1
Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
07/11/2003
1.2
same as that for all other Spartan-3 devices. Updated description of I/O voltage tolerance in
ESDProtection section. In
Table 10, changed input termination type for DCI version of the LVCMOS standard
to None. Added additional flexibility for making DLL connections in
Figure 21 and accompanying text. In
the
Configuration section, inserted an explanation of how to choose power supplies for the configuration
interface, including guidelines for achieving 3.3V-tolerance.
08/24/2004
1.3
Showed inversion of 3-state signal
(Figure 7). Clarified description of pull-up and pull-down resistors
output buffer name in
Figure 21. Corrected description of how DOUT is synchronized to CCLK (
page 47).08/19/2005
1.4
Corrected description of WRITE_FIRST and READ_FIRST in
Table 13. Added note regarding address
setup and hold time requirements whenever a block RAM port is enabled
(Table 13). Added information
because its timing is not programmable.
04/03/2006
2.0
04/26/2006
2.1
Added more information on the pull-up resistors that are active during configuration to
Configuration.JTAG if the mode select pins are set for other than JTAG.
05/25/2007
2.2
Table 11. Added note that pull-down is active during boundary scan tests.
11/30/2007
2.3
Updated links to documentation on xilinx.com.
06/25/2008
2.4
Added HSLVDCI to
Table 10. Updated formatting and links.
12/04/2009
2.5
differential signaling VCCO values in Table 10. Noted that the CP132 package is being discontinued in The 10/29/2012
3.0
discussion throughout document. Per
XCN08011, updated the discontinued CP132 and CPG132
package discussion throughout document. This product is not recommended for new designs.
06/27/2013
3.1
Removed banner. This product IS recommended for new designs.