参数资料
| 型号： | XC4010E-4PQ208C |
| 厂商： | Xilinx Inc |
| 文件页数： | 30/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 400 CLB'S 208-PQFP |
| 产品变化通告： | Product Discontinuation 28/Jul/2010 |
| 标准包装： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 400 |
| 逻辑元件/单元数： | 950 |
| RAM 位总计： | 12800 |
| 输入/输出数： | 160 |
| 门数： | 10000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
| 其它名称： | 122-1107 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-40
May 14, 1999 (Version 1.6)
Table 16: Pin Descriptions
Pin Name
I/O
During
Cong.
I/O
After
Cong.
Pin Description
Permanently Dedicated Pins
VCC
I
Eight or more (depending on package) connections to the nominal +5 V supply voltage
(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1
F capacitor to Ground.
GND
I
Eight or more (depending on package type) connections to Ground. All must be con-
nected.
CCLK
I or O
I
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral
mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the
Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-
vices, except during Readback. See “Violating the Maximum High and Low Time Spec-
ification for the Readback Clock” on page 56 for an explanation of this exception.
DONE
I/O
O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the XACT
step program that cre-
ates the configuration bitstream. The resistor is included by default.
PROGRAM
I
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
RDY/BUSY
O
I/O
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
RCLK
O
I/O
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is
useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
M0, M1, M2
I
I (M0),
O (M1),
I (M2)
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
During configuration, these pins have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 k
is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
TDO
O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| A1225A-1PQG100I | IC FPGA 2500 GATES 100-PQFP IND |
| IDT71V416L15BEGI8 | IC SRAM 4MBIT 15NS 48FBGA |
| XC4025E-2HQ240C | IC FPGA 1024 CLB'S 240-HQFP |
| IDT71V416L12BEGI8 | IC SRAM 4MBIT 12NS 48FBGA |
| XC4020E-3HQ240C | IC FPGA 784 CLB'S 240-HQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4010E-4PQ208C0262 | 制造商:Xilinx 功能描述: |
| XC4010E-4PQ208C0377 | 制造商:Xilinx 功能描述: |
| XC4010E-4PQ208C0432 | 制造商:Xilinx 功能描述: |
| XC4010E-4PQ208I | 功能描述:IC FPGA I-TEMP 5V 4SPD 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4010L-5PC84C | 功能描述:IC 3.3V FPGA 400 CLB'S 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000 标准包装:24 系列:ECP2 LAB/CLB数:1500 逻辑元件/单元数:12000 RAM 位总计:226304 输入/输出数:131 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） |
发布紧急采购，3分钟左右您将得到回复。