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参数资料
| 型号： | XC4013E-1HG240C |
| 厂商： | Xilinx, Inc. |
| 英文描述： | Programmable Gate Arrays |
| 中文描述： | 可编程门阵列 |
| 文件页数： | 47/68页 |
| 文件大小： | 462K |
| 代理商： | XC4013E-1HG240C |
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R
May 14, 1999 (Version 1.6)
6-55
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Readback
The user can read back the content of conguration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded conguration
bits, but can also include the present state of the device,
represented by the content of all ip-ops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Note that in XC4000 Series devices, conguration data is
not inverted with respect to conguration as it is in XC2000
and XC3000 families.
XC4000 Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, place the READ-
BACK library symbol and attach the appropriate pad sym-
bols, as shown in Figure 49.
After Readback has been initiated by a High level on
RDBK.TRIG after conguration, the RDBK.RIP (Read In
Progress) output goes High on the next rising edge of
RDBK.CLK. Subsequent rising edges of this clock shift out
Readback data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with ve dummy bits (all High) followed by the Start bit
(Low) of the rst frame. The rst two data bits of the rst
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
DONE
*
**
QS
R
1
0
1
0
1
0
1
0
1
GSR ENABLE
GSR INVERT
STARTUP.GSR
STARTUP.GTS
GTS INVERT
GTS ENABLE
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
Q2
Q3
Q1/Q4
DONE
IN
STARTUP
Q0
Q1
Q2
Q3
Q4
M
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
K
SQ
K
DQ
K
DQ
K
DQ
K
DQ
FULL
LENGTH COUNT
CLEAR MEMORY
CCLK
STARTUP.CLK
USER NET
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
X1528
Figure 48: Start-up Logic
相关PDF资料 |
PDF描述 |
|---|---|
| XC4013E-3BG240M | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-1VQ240M | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-2BG240C | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-2BG240I | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-2BG240M | XC4000E and XC4000X Series Field Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4013E-1HG240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-1HG240M | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-1HQ208C | 功能描述:IC FPGA C-TEMP 5V 1SPD 208-HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4013E-1HQ208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4013E-1HQ240C | 功能描述:IC FPGA C-TEMP 5V 1SPD 240-HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
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