- 您现在的位置：买卖IC网 > PDF目录277724 > XC4013E-2BGG225I (XILINX INC) FPGA, 576 CLBS, 10000 GATES, 125 MHz, PBGA225 PDF资料下载
参数资料
| 型号： | XC4013E-2BGG225I |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PBGA225 |
| 文件页数： | 12/17页 |
| 文件大小： | 75K |
| 代理商： | XC4013E-2BGG225I |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-104
February 11, 2000 (Version 1.8)
Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions.
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Device
Max
TBUF driving a Horizontal Longline (LL):
I going High or Low to LL going High or
Low, while T is Low.
Buffer is constantly active.
(Note1)
TIO1
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
6.0
7.0
8.0
9.0
10.0
11.0
4.2
5.0
5.9
6.3
6.4
7.2
8.2
9.1
3.4
4.0
4.7
5.0
5.1
5.7
7.3
2.9
3.4
4.0
4.3
4.4
4.9
5.6
–
ns
I going Low to LL going from resistive
pull-up High to active Low.
TBUF configured as open-drain.
(Note1)
TIO2
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
6.0
7.8
8.1
10.5
11.0
12.0
4.2
5.3
6.4
6.8
6.9
7.7
8.7
9.6
3.6
4.5
5.4
5.8
5.9
6.5
8.7
9.6
3.1
3.8
4.6
4.9
5.0
5.5
7.4
–
ns
T going Low to LL going from resistive
pull-up or floating High to active Low.
TBUF configured as open-drain or active
buffer with I = Low.
(Note1)
TON
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
7.0
7.5
8.0
8.5
8.7
11.0
4.6
6.0
6.7
7.1
7.3
7.5
8.4
3.9
5.7
6.0
6.2
7.0
7.1
3.5
4.7
4.9
5.2
5.4
6.2
6.3
–
ns
T going High to TBUF going inactive,
not driving LL
TOFF
All devices
1.8
1.5
1.3
1.1
ns
T going High to LL going from Low to
High, pulled up by a single resistor.
(Note 1)
TPUS
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
20.0
23.0
25.0
27.0
29.0
32.0
35.0
42.0
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
12.0
14.0
16.0
18.0
21.0
26.0
–
ns
T going High to LL going from Low to
High, pulled up by two resistors.
(Note1)
TPUF
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.0
10.0
11.5
12.5
13.5
15.0
16.0
18.0
7.0
8.0
9.0
10.0
11.0
13.0
14.8
16.5
6.0
6.8
7.7
8.5
9.4
11.7
14.8
16.5
5.4
5.8
6.5
7.5
8.0
9.4
10.5
–
ns
Note 1: These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
相关PDF资料 |
PDF描述 |
|---|---|
| XC4013E-3HQG240C | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP240 |
| XC4013E-3HQG240I | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP240 |
| XC4013E-4HQG240C | FPGA, 576 CLBS, 10000 GATES, 111 MHz, PQFP240 |
| XC4013E-4HQG240I | FPGA, 576 CLBS, 10000 GATES, 111 MHz, PQFP240 |
| XC4013E-3HQG208C | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4013E-2CB240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2CB240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2CB240M | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。