参数资料
| 型号： | XC4020E-2HQ240I |
| 厂商： | Xilinx Inc |
| 文件页数： | 1/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 5V 2SPD 240-HQFP |
| 产品变化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 标准包装： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 784 |
| 逻辑元件/单元数： | 1862 |
| RAM 位总计： | 25088 |
| 输入/输出数： | 193 |
| 门数： | 20000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP 裸露焊盘 |
| 供应商设备封装： | 240-PQFP（32x32） |
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May 14, 1999 (Version 1.6)
6-5
6
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx web site at
System featured Field-Programmable Gate Arrays
-
SelectRAMTM memory: on-chip ultra-fast RAM with
-
synchronous write option
-
dual-port RAM option
-
Fully PCI compliant (speed grades -2 and faster)
-
Abundant ip-ops
-
Flexible function generators
-
Dedicated high-speed carry logic
-
Wide edge decoders on each edge
-
Hierarchy of interconnect lines
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal distribution
networks
System Performance beyond 80 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
-
IEEE 1149.1-compatible boundary scan logic
support
-
Individually programmable output slew rate
-
Programmable input pull-up or pull-down resistors
-
12 mA sink current per XC4000E output
Congured by Loading Binary File
-
Unlimited re-programmability
Read Back Capability
-
Program verication
-
Internal node observability
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
-
Interfaces to popular design environments
-
Fully automatic mapping, placement and routing
-
Interactive design editor for design optimization
Low-Voltage Versions Available
Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Additional XC4000X Series Features
High Performance — 3.3 V XC4000XL
High Capacity — Over 180,000 Usable Gates
5 V tolerant I/Os on XC4000XL
0.35
m SRAM process for XC4000XL
Additional Routing Over XC4000E
-
almost twice the routing capacity for high-density
designs
Buffered Interconnect for Maximum Speed Blocks
Improved VersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
12 mA Sink Current Per XC4000X Output
Flexible New High-Speed Clock Network
-
Eight additional Early Buffers for shorter clock delays
-
Virtually unlimited number of clock signals
Optional Multiplexer or 2-input Function Generator on
Device Outputs
Four Additional Address Bits in Master Parallel
Conguration Mode
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benets of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 1.
0
XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6)
00*
Product Specification
R
Product Obsolete or Under Obsolescence
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