参数资料
| 型号： | XC4028EX-3HQ208C |
| 厂商： | Xilinx Inc |
| 文件页数： | 35/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1024 CLB'S 208-HQFP |
| 标准包装： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 1024 |
| 逻辑元件/单元数： | 2432 |
| RAM 位总计： | 32768 |
| 输入/输出数： | 160 |
| 门数： | 28000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 208-BFQFP 裸露焊盘 |
| 供应商设备封装： | 208-PQFP（28x28） |
| 其它名称： | 122-1127 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-44
May 14, 1999 (Version 1.6)
Instruction Set
The XC4000 Series boundary scan instruction set also
includes instructions to congure the device and read back
the conguration data. The instruction set is coded as
shown in Table 17.
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only M0 and M2 mode pins contribute only the In bit
to the boundary scan I/O data register, while the out-
put-only M1 pin contributes all three bits.
The rst two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The nal bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in XDE or
Epic), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 42.
The device-specic pinout tables for the XC4000 Series
include the boundary scan locations for each IOB pin.
BSDL (Boundary Scan Description Language) les for
XC4000 Series devices are available on the Xilinx FTP site.
Including Boundary Scan in a Schematic
If boundary scan is only to be used during conguration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after conguration.
To indicate that boundary scan remain enabled after cong-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 43.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
D
Q
D
Q
IOB
M
U
X
BYPASS
REGISTER
IOB
TDO
TDI
IOB
1
0
1
0
1
0
1
0
1
0
sd
LE
DQ
D
Q
D
Q
1
0
1
0
1
0
1
0
DQ
LE
sd
LE
DQ
sd
LE
DQ
IOB
D
Q
1
0
DQ
LE
sd
IOB.T
DATA IN
IOB.I
IOB.Q
IOB.T
IOB.I
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
DATAOUT
UPDATE
EXTEST
X9016
INSTRUCTION REGISTER
Figure 41: XC4000 Series Boundary Scan Logic
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| XC4028EX-2HQ208C | IC FPGA 1024 CLB'S 208-HQFP |
| IDT71V424L15PHGI8 | IC SRAM 4MBIT 15NS 44TSOP |
| IDT7164S25YGI | IC SRAM 64KBIT 25NS 28SOJ |
| XC4025E-3HQ240C | IC FPGA 1024 CLB'S 240-HQFP |
| XC4013E-3PQ160C | IC FPGA 576 CLB'S 160-PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4028EX-3HQ208I | 制造商:Xilinx 功能描述: |
| XC4028EX-3HQ240C | 制造商:Xilinx 功能描述: |
| XC4028EX-3HQ240I | 制造商:Xilinx 功能描述: |
| XC4028EX-3HQ304C | 制造商:Xilinx 功能描述: |
| XC4028EX-4BG352I | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:FPGA, 1024 CLBS, 18000 GATES, 143 MHz, PBGA352 |
发布紧急采购，3分钟左右您将得到回复。