参数资料
| 型号： | XC4044XL-2HQ160C |
| 厂商： | Xilinx Inc |
| 文件页数： | 37/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA C-TEMP 3.3V 2SPD 160HQFP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 1600 |
| 逻辑元件/单元数： | 3800 |
| RAM 位总计： | 51200 |
| 输入/输出数： | 129 |
| 门数： | 44000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 160-BQFP 裸露焊盘 |
| 供应商设备封装： | 160-PQFP（28x28） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-46
May 14, 1999 (Version 1.6)
Conguration Modes
XC4000E devices have six conguration modes. XC4000X
devices have the same six modes, plus an additional con-
guration mode. These modes are selected by a 3-bit input
code applied to the M2, M1, and M0 inputs. There are three
self-loading Master modes, two Peripheral modes, and a
Serial
Slave
mode,
which
is
used
primarily
for
daisy-chained devices. The coding for mode selection is
shown in Table 18.
A detailed description of each conguration mode, with tim-
ing information, is included later in this data sheet. During
conguration, some of the I/O pins are used temporarily for
the conguration process. All pins used during congura-
tion are shown in Table 22 on page 58.
Master Modes
The three Master modes use an internal oscillator to gener-
ate a Conguration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for exter-
nal PROM(s) containing the conguration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel data.
The data is internally serialized into the FPGA data-frame
format. The up and down selection generates starting
addresses at either zero or 3FFFF (3FFFFF when 22
address lines are used), for compatibility with different
microprocessor addressing conventions. The Master Serial
mode generates CCLK and receives the conguration data
in serial form from a Xilinx serial-conguration PROM.
CCLK speed is selectable as either 1 MHz (default) or 8
MHz. Conguration always starts at the default slow fre-
quency, then can switch to the higher frequency during the
rst frame. Frequency tolerance is -50% to +25%.
Additional Address lines in XC4000 devices
The XC4000X devices have additional address lines
(A18-A21) allowing the additional address space required
to daisy-chain several large devices.
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address lines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL device.
The additional address lines (A18-A21) are not available in
the PC84 package.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sig-
nal. In Asynchronous Peripheral mode, the internal oscilla-
tor generates a CCLK burst signal that serializes the
byte-wide data. CCLK can also drive slave devices. In the
synchronous mode, an externally supplied clock input to
CCLK serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial congura-
tion data on the rising edge of CCLK and, after loading its
conguration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Multiple slave devices with identical congurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be congured simultaneously.
Serial Daisy Chain
Multiple devices with different congurations can be con-
nected together in a “daisy chain,” and a single combined
bitstream used to congure the chain of slave devices.
To congure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 51 on page
60. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each
passes resynchronized conguration data coming from a
single source. The header data, including the length count,
Table 18: Conguration Modes
Mode
M2
M1
M0
CCLK
Data
Master Serial
0
output
Bit-Serial
Slave Serial
1
input
Bit-Serial
Master
Parallel Up
1
0
output
Byte-Wide,
increment
from 00000
Master
Parallel Down
1
0
output
Byte-Wide,
decrement
from 3FFFF
Peripheral
Synchronous*
0
1
input
Byte-Wide
Peripheral
Asynchronous
1
0
1
output
Byte-Wide
Reserved
0
1
0
—
Reserved
0
1
—
* Can be considered byte-wide Slave Parallel
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| KMPC850DECVR66BU | IC MPU PWRQUICC 66MHZ 256-PBGA |
| RMC40DTEH | CONN EDGECARD 80POS .100 EYELET |
| IDT70V9389L9PRFI8 | IC SRAM 1.125MBIT 9NS 128TQFP |
| KMPC8343EZQAGD | IC MPU PWRQUICC II 620-PBGA |
| ASM28DREN | CONN EDGECARD 56POS .156 EYELET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4044XL-2HQ160I | 功能描述:IC FPGA I-TEMP 3.3V 2SPD 160HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4044XL2HQ208C | 制造商:XILINX 功能描述:* |
| XC4044XL-2HQ208C | 功能描述:IC FPGA C-TEMP 3.3V 2SPD 208HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4044XL-2HQ208I | 功能描述:IC FPGA I-TEMP 3.3V 2SPD 208HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XC4044XL2HQ240 | 制造商:n/a 功能描述:_ |
发布紧急采购，3分钟左右您将得到回复。