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参数资料
| 型号： | XC5204-6PG191C |
| 厂商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 现场可编程门阵列 |
| 文件页数： | 10/73页 |
| 文件大小： | 598K |
| 代理商： | XC5204-6PG191C |
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XC5200 Series Field Programmable Gate Arrays
7-100
November 5, 1998 (Version 5.2)
XC5200-Series devices can also be configured through the
boundary scan logic. See XAPP 017 for more information.
Data Registers
The primary data register is the boundary scan register.
For each IOB pin in the FPGA, bonded or not, it includes
three bits for In, Out and 3-State Control. Non-IOB pins
have appropriate partial bit population for In or Out only.
PROGRAM, CCLK and DONE are not included in the
boundary scan register.
Each EXTEST CAPTURE-DR
state captures all In, Out, and 3-State pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions, USER1 and USER2.
For
these
instructions,
two
corresponding
pins
(BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to
be shifted out on TDO.
The data register clock
(BSCAN.DRCK) is available for control of test logic which
the user may wish to implement with CLBs. The NAND of
TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).
Instruction Set
The XC5200-Series boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 7.
Table 7: Boundary Scan Instructions
Bit Sequence
The bit sequence within each IOB is: 3-State, Out, In. The
data-register cells for the TAP pins TMS, TCK, and TDI
have an OR-gate that permanently disables the output
buffer if boundary-scan operation is selected. Conse-
quently, it is impossible for the outputs in IOBs used by TAP
inputs to conflict with TAP operation. TAP data is taken
directly from the pin, and cannot be overwritten by injected
boundary-scan data.
The primary global clock inputs (PGCK1-PGCK4) are
taken directly from the pins, and cannot be overwritten with
boundary-scan data. However, if necessary, it is possible to
drive the clock input from boundary scan. The external
clock source is 3-stated, and the clock net is driven with
boundary scan data through the output driver in the
clock-pad IOB. If the clock-pad IOBs are used for non-clock
signals, the data may be overwritten normally.
Pull-up and pull-down resistors remain active during
boundary scan. Before and during configuration, all pins
are pulled up. After configuration, the choice of internal
pull-up or pull-down resistor must be taken into account
when designing test vectors to detect open-circuit PC
traces.
From a cavity-up view of the chip (as shown in XDE or
Epic), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Table 8.
The device-specific pinout tables for the XC5200 Series
include the boundary scan locations for each IOB pin.
Table 8: Boundary Scan Bit Sequence
BSDL (Boundary Scan Description Language) files for
XC5200-Series devices are available on the Xilinx web site
in the File Download area.
Including Boundary Scan
If boundary scan is only to be used during configuration, no
special elements need be included in the schematic or HDL
code. In this case, the special boundary scan pins TDI,
TMS, TCK and TDO can be used for user functions after
configuration.
To indicate that boundary scan remain enabled after config-
uration, include the BSCAN library symbol and connect pad
symbols to the TDI, TMS, TCK and TDO pins, as shown in
Instruction I2
I1
I0
Test
Selected
TDO Source
I/O Data
Source
0
EXTEST
DR
0
1
SAMPLE/PR
ELOAD
DR
Pin/Logic
0
1
0
USER 1
BSCAN.
TDO1
User Logic
0
1
USER 2
BSCAN.
TDO2
User Logic
1
0
READBACK
Readback
Data
Pin/Logic
1
0
1
CONFIGURE
DOUT
Disabled
1
0
Reserved
——
1
BYPASS
Bypass
Register
—
Bit Position
I/O Pad Location
Bit 0 (TDO)
Top-edge I/O pads (right to left)
Bit 1
...
Left-edge I/O pads (top to bottom)
...
Bottom-edge I/O pads (left to right)
...
Right-edge I/O pads (bottom to top)
Bit N (TDI)
BSCANT.UPD
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| XC5204-6PQ100I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5204-6PQ160C | 功能描述:IC FPGA 120 CLB'S 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC5200 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
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