参数资料
型号: XC5VLX30-1FFG324CES
厂商: Xilinx Inc
文件页数: 58/91页
文件大小: 0K
描述: IC FPGA VIRTEX-5 ES 30K 324-FBGA
标准包装: 1
系列: Virtex®-5 LX
LAB/CLB数: 2400
逻辑元件/单元数: 30720
RAM 位总计: 1179648
输入/输出数: 220
电源电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 324-BBGA,FCBGA
供应商设备封装: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
61
Table 81: Miscellaneous Timing Parameters
Symbol
Description
Speed Grade
-3
-2
-1
Units
Time Required to Achieve LOCK
TDLL_240
DLL output – Frequency range > 240 MHz (1)
80.00
s
TDLL_120_240
DLL output – Frequency range 120 - 240 MHz (1)
250.00
s
TDLL_60_120
DLL output – Frequency range 60 - 120 MHz (1)
900.00
s
TDLL_50_60
DLL output – Frequency range 50 - 60 MHz(1)
1300.00
s
TDLL_40_50
DLL output – Frequency range 40 - 50 MHz (1)
2000.00
s
TDLL_30_40
DLL output – Frequency range 30 - 40 MHz (1)
3600.00
s
TDLL_24_30
DLL output – Frequency range 24 - 30 MHz(1)
5000.00
s
TDLL_30
DLL output – Frequency range < 30 MHz (1)
5000.00
s
TFX_MIN
DFS outputs(2)
10.00
ms
TFX_MAX
10.00
ms
TDLL_FINE_SHIFT
Multiplication factor for DLL lock time with Fine Shift
2.00
Fine Phase Shifting
TRANGE_MS
Absolute shifting range in maximum speed mode
7.00
ns
TRANGE_MR
Absolute shifting range in maximum range mode
10.00
ns
Delay Lines
TTAP_MS_MIN
Tap delay resolution (Min) in maximum speed mode
7.00
ps
TTAP_MS_MAX
Tap delay resolution (Max) in maximum speed mode
30.00
ps
TTAP_MR_MIN
Tap delay resolution (Min) in maximum range mode
10.00
ps
TTAP_MR_MAX
Tap delay resolution (Max) in maximum range mode
40.00
ps
Notes:
1.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY
2
33
CLKFX_DIVIDE
1
32
Table 83: DCM Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
TDMCCK_PSEN/ TDMCKC_PSEN
PSEN Setup/Hold
1.20
0.00
1.35
0.00
1.56
0.00
ns
TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC
PSINCDEC Setup/Hold
1.20
0.00
1.35
0.00
1.56
0.00
ns
TDMCKO_PSDONE
Clock to out of PSDONE
1.00
1.12
1.30
ns
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