参数资料
型号: XC5VLX330T-1FFG1738I
厂商: Xilinx Inc
文件页数: 38/91页
文件大小: 0K
描述: IC FPGA VIRTEX-5 330K 1738FBGA
标准包装: 1
系列: Virtex®-5 LXT
LAB/CLB数: 25920
逻辑元件/单元数: 331776
RAM 位总计: 11943936
输入/输出数: 960
电源电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 1738-BBGA,FCBGA
供应商设备封装: 1738-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML525-FXT-UNI-G-J-ND - EVAL BD ROCKETIO GTX VIRTEX5 JPN
HW-V5-ML525-FXT-UNI-G-ND - EVAL BOARD ROCKETIO GTX VIRTEX5
HW-V5-ML525-UNI-G-ND - EVAL PLATFORM ROCKET IO VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
43
Output Serializer/Deserializer Switching Characteristics
Table 63: OSERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
0.21
–0.02
0.24
–0.02
0.30
–0.02
ns
TOSDCK_T/TOSCKD_T(1)
T input Setup/Hold with respect to CLK
0.28
–0.18
0.34
–0.18
0.41
–0.18
ns
TOSDCK_T2/TOSCKD_T2(1)
T input Setup/Hold with respect to CLKDIV
0.21
–0.03
0.24
–0.03
0.28
–0.03
ns
TOSCCK_OCE/TOSCKC_OCE
OCE input Setup/Hold with respect to CLK
0.16
–0.07
0.19
–0.07
0.23
–0.07
ns
TOSCCK_S
SR (Reset) input Setup with respect to CLKDIV
0.52
0.58
0.70
ns
TOSCCK_TCE/TOSCKC_TCE
TCE input Setup/Hold with respect to CLK
0.20
–0.06
0.23
–0.06
0.29
–0.06
ns
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
0.59
0.60
0.61
ns
TOSCKO_TQ
Clock to out from CLK to TQ
0.61
0.62
ns
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.62
0.70
0.83
ns
TOSCO_OQ
Asynchronous Reset to OQ
1.57
1.82
2.19
ns
TOSCO_TQ
Asynchronous Reset to TQ
1.63
1.89
2.27
ns
Notes:
1.
TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
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