参数资料
型号: XC6SLX75T-2FG676I
厂商: Xilinx Inc
文件页数: 41/89页
文件大小: 0K
描述: IC FPGA SPARTAN 6 676FGGBGA
标准包装: 40
系列: Spartan® 6 LXT
LAB/CLB数: 5831
逻辑元件/单元数: 74637
RAM 位总计: 3170304
输入/输出数: 348
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
46
Input Serializer/Deserializer Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 37: ISERDES2 Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
0.16/
–0.09
0.20/
–0.09
0.31/
–0.09
0.34/
–0.14
ns
TISCCK_CE / TISCKC_CE
CE pin Setup/Hold with respect to CLK
0.71/
–0.47
0.71/
–0.42
0.97/
–0.42
1.39/
–0.71
ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.24/
–0.15
0.25/
–0.05
0.29/
–0.05
0.09/
–0.05
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IODELAY2)
–0.25/
0.30
–0.25/
0.42
–0.25/
0.56
–0.54/
0.67
ns
TISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at DDR mode
–0.03/
0.04
–0.03/
0.16
–0.03/
0.18
–0.05/
0.12
ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY2)
–0.40/
0.48
–0.40/
0.53
–0.40/
0.71
–0.71/
0.86
ns
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
1.30
1.44
2.02
2.22
ns
FCLKDIV
CLKDIV maximum frequency
270
262.5
250
125
MHz
Table 38: OSERDES2 Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
–0.03/
1.02
–0.03/
1.17
–0.03/
1.27
–0.02/
0.23
ns
TOSDCK_T/TOSCKD_T(1)
T input Setup/Hold with respect to CLK
–0.05/
1.03
–0.05/
1.13
–0.05/
1.23
–0.05/
0.24
ns
TOSCCK_OCE/TOSCKC_OCE
OCE input Setup/Hold with respect to CLK
0.12/
–0.03
0.15/
–0.03
0.24/
–0.03
0.28/
–0.17
ns
TOSCCK_TCE/TOSCKC_TCE
TCE input Setup/Hold with respect to CLK
0.14/
–0.08
0.17/
–0.08
0.27/
–0.08
0.31/
–0.16
ns
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
0.94
1.11
1.51
1.89
ns
TOSCKO_TQ
Clock to out from CLK to TQ
0.94
1.11
1.51
1.91
ns
FCLKDIV
CLKDIV maximum frequency
270
262.5
250
125
MHz
Notes:
1.
TOSDCK_T2/TOSCKD_T2 (T input setup/hold with respect to CLKDIV) are reported as TOSDCK_T/TOSCKD_T in TRACE report.
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