参数资料
型号: XC6SLX75T-3FG484I
厂商: Xilinx Inc
文件页数: 42/89页
文件大小: 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
标准包装: 60
系列: Spartan® 6 LXT
LAB/CLB数: 5831
逻辑元件/单元数: 74637
RAM 位总计: 3170304
输入/输出数: 268
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BBGA
供应商设备封装: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
47
Input/Output Delay Switching Characteristics
Table 39: IODELAY2 Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L(3)
TIODCCK_CAL / TIODCKC_CAL
CAL pin Setup/Hold with respect to CK
0.28/
–0.13
0.33/
–0.13
0.48/
–0.13
N/A
ns
TIODCCK_CE / TIODCKC_CE
CE pin Setup/Hold with respect to CK
0.17/
–0.03
0.17/
–0.03
0.25/
–0.02
N/A
ns
TIODCCK_INC/ TIODCKC_INC
INC pin Setup/Hold with respect to CK
0.10/
0.02
0.12/
0.03
0.18/
0.06
N/A
ns
TIODCCK_RST/ TIODCKC_RST
RST pin Setup/Hold with respect to CK
0.12/
–0.02
0.15/
–0.02
0.22/
–0.01
N/A
ns
Maximum tap 1 delay
8
14
16
N/A
ps
TTAP2
Maximum tap 2 delay
40
66
77
N/A
ps
TTAP3
Maximum tap 3 delay
95
120
140
N/A
ps
TTAP4
Maximum tap 4 delay
108
141
166
N/A
ps
TTAP5
Maximum tap 5 delay
171
194
231
N/A
ps
TTAP6
Maximum tap 6 delay
207
249
292
N/A
ps
TTAP7
Maximum tap 7 delay
212
276
343
N/A
ps
TTAP8
Maximum tap 8 delay
322
341
424
N/A
ps
FMINCAL
Minimum allowed bit rate for calibration in variable
mode: VARIABLE_FROM_ZERO,
VARIABLE_FROM_HALF_MAX, and
DIFF_PHASE_DETECTOR.
188
N/A
Mb/s
TIODDO_IDATAIN
Propagation delay through IODELAY2
TIODDO_ODATAIN
Propagation delay through IODELAY2
Notes:
1.
Delay depends on IODELAY2 tap setting. See TRACE report for actual values.
2.
Maximum delay = integer (number of taps/8)
T
TAP8 +TTAPn (where n equals the remainder). For minimum delay consult the TRACE setup
and hold report. Minimum delay is typically greater than 30% of the maximum delay. Tap delays can vary by device and overall conditions.
See TRACE report for actual values.
3.
Spartan-6 -1L devices only support tap 0. See TRACE report for actual values.
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