参数资料
型号: XC6VCX240T-2FFG1156C
厂商: Xilinx Inc
文件页数: 14/52页
文件大小: 0K
描述: IC FPGA VIRTEX 6 241K 1156FFGBGA
产品培训模块: Virtex-6 FPGA Overview
产品变化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
标准包装: 1
系列: Virtex® 6 CXT
LAB/CLB数: 18840
逻辑元件/单元数: 241152
RAM 位总计: 15335424
输入/输出数: 600
电源电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 1156-BBGA,FCBGA
供应商设备封装: 1156-FCBGA(35x35)
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
21
Table 30: GTX Transceiver User Clock Switching Characteristics(1)
Symbol
Description
Conditions
Speed Grade
Units
-2
-1
FTXOUT
TXOUTCLK maximum frequency
Internal 20-bit data path
187.5
MHz
Internal 16-bit data path
234.38
MHz
FRXREC
RXRECCLK maximum frequency
Internal 20-bit data path
187.5
MHz
Internal 16-bit data path
234.38
MHz
TRX
RXUSRCLK maximum frequency
234.38
MHz
TRX2
RXUSRCLK2 maximum frequency
1 byte interface
376
312.5
MHz
2 byte interface
234.38
MHz
4 byte interface
117.19
MHz
TTX
TXUSRCLK maximum frequency
234.38
MHz
TTX2
TXUSRCLK2 maximum frequency
1 byte interface
376
312.5
MHz
2 byte interface
234.38
MHz
4 byte interface
117.19
MHz
Notes:
1.
Clocking must be implemented as described in Virtex-6 FPGA GTX Transceivers User Guide.
Table 31: GTX Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max
Units
FGTXTX
Serial data rate range
0.480
FGTXMAX
Gb/s
TRTX
TX Rise time
20%–80%
120
ps
TFTX
TX Fall time
80%–20%
120
ps
TLLSKEW
TX lane-to-lane skew(1)
350
ps
VTXOOBVDPP
Electrical idle amplitude
15
mV
TTXOOBTRANSITION
Electrical idle transition time
75
ns
TJ3.75
3.75 Gb/s
0.34
UI
DJ3.75
Deterministic Jitter(2)(3)
0.16
UI
TJ3.125
3.125 Gb/s
0.2
UI
DJ3.125
Deterministic Jitter(2)(3)
––
0.1
UI
TJ3.125L
3.125 Gb/s(4)
0.35
UI
DJ3.125L
Deterministic Jitter(2)(3)
0.16
UI
TJ2.5
2.5 Gb/s(5)
0.20
UI
DJ2.5
Deterministic Jitter(2)(3)
0.08
UI
TJ1.25
1.25 Gb/s(6)
0.15
UI
DJ1.25
Deterministic Jitter(2)(3)
0.06
UI
TJ600
600 Mb/s
0.1
UI
DJ600
Deterministic Jitter(2)(3)
0.03
UI
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