参数资料
| 型号： | XC6VSX315T-2FF1759I |
| 厂商： | Xilinx Inc |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX-6SXT 1759FFBGA |
| 产品培训模块： | Virtex-6 FPGA Overview |
| 产品变化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 标准包装： | 12 |
| 系列： | Virtex® 6 SXT |
| LAB/CLB数： | 24600 |
| 逻辑元件/单元数： | 314880 |
| RAM 位总计： | 25952256 |
| 输入/输出数： | 720 |
| 电源电压： | 0.95 V ~ 1.05 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 1759-BBGA，FCBGA |
| 供应商设备封装： | 1759-FCBGA |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
6
Block RAM
Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two
completely independent ports that share nothing but the stored data.
Synchronous Operation
Each memory access, read and write, is controlled by the clock. All inputs, data, address, clock enables, and write enables
are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation.
An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation, the data output can reflect either the previously stored data, the newly written data, or remain
unchanged.
Programmable Data Width
Each port can be configured as 32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 2K × 18 (or 16), 1K × 36 (or 32), or 512 x 72
(or 64). The two ports can have different aspect ratios, without any constraints.
Each block RAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any
aspect ratio from 16K x 1 to 512 x 36. Everything described previously for the full 36 Kb block RAM also applies to each
of the smaller 18 Kb block RAMs.
In 18 Kb block RAMs, only simple dual-port mode can provide data width of >36 bits. In this mode, one port is
dedicated to read and the other port is dedicated to write operation. In SDP mode one side (read or write) can be
variable while the other is fixed to 32/36 or 64/72. There is no read output during write. The dual-port 36 Kb RAM both
sides can be of variable width.
Two adjacent 36 Kb block RAMs can be configured as one cascaded 64K × 1 dual-port RAM without any additional
logic.
Error Detection and Correction
Each 64 bit-wide block RAM can generate, store, and utilize eight additional Hamming-code bits, and perform single-bit error
correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to,
or reading from external 64/72-wide memories. This works in simple dual-port mode and does not support read-during-write.
FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments
the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and
almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the
write and read ports always have identical width. First-word fall-through mode presents the first-written word on the data
output even before the first read operation. After the first word has been read, there is no difference between this mode and
the standard mode.
Digital Signal Processing—DSP48E1 Slice
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All Virtex-6
FPGAs have many dedicated, full-custom, low-power DSP slices combining high speed with small size, while retaining
system design flexibility.
Each DSP48E1 slice fundamentally consists of a dedicated 25 × 18 bit two's complement multiplier and a 48-bit
accumulator, both capable of operating at 600 MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can
feed a single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit
add/subtract/accumulate), or a logic unit that can generate any one of 10 different logic functions of the two operands.
The DSP48E1 includes an additional pre-adder, typically used in symmetrical filters. This new pre-adder improves
performance in densely packed designs and reduces the logic slice count by up to 50%.
The DSP48E1 slice provides extensive pipelining and extension capabilities that enhance speed and efficiency of many
applications, even beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide
bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down
counter. The multiplier can perform logic functions (AND, OR) and barrel shifting.
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| XC6VSX315T-2FFG1156C | 功能描述:IC FPGA VIRTEX 6 314K 1156FFGBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex® 6 SXT 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC6VSX315T-2FFG1156I | 功能描述:IC FPGA VIRTEX 6 314K 1156FFGBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex® 6 SXT 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC6VSX315T-2FFG1759C | 功能描述:IC FPGA VIRTEX 6 314K 1759FFGBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex® 6 SXT 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC6VSX315T-2FFG1759I | 功能描述:IC FPGA VIRTEX 6 314K 1759FFGBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex® 6 SXT 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC6VSX315T-3FF1156C | 制造商:Xilinx 功能描述:VIRTEX6SXT - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA |
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