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参数资料
| 型号： | XC95288XV-7PQ208C |
| 厂商： | XILINX INC |
| 元件分类： | PLD |
| 英文描述： | High-Performance CPLD |
| 中文描述： | FLASH PLD, 7.5 ns, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 1/14页 |
| 文件大小： | 133K |
| 代理商： | XC95288XV-7PQ208C |
DS050 (v3.0) June 25, 2007
1
Product Specification
2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
u
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC95288XV devices with equivalent XC95288XL
devices in all designs as soon as possible. Recommended
replacements are pin compatible, however require a VCC
change to 3.3V, and a recompile of the design file. In addi-
tion, there is no 1.8V I/O support, and only one output bank
is supported. See XCN07010 for details regarding this dis-
continuation, including device replacement recomendations
for the XC95288XV CPLD.
Features
288 macrocells with 6,400 usable gates
Available in small footprint packages
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144-pin TQFP (117 user I/O pins)
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208-pin PQFP (168 user I/O pins)
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280-pin CSP (192 user I/O pins)
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256-pin FBGA (192 user I/O pins)
Optimized for high-performance 2.5V systems
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Low power operation
-
Multi-voltage operation
Advanced system features
-
In-system programmable
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Four separate output banks
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Superior pin-locking and routability with
Fast CONNECT II switch matrix
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Extra wide 54-input Function Blocks
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Up to 90 product-terms per macrocell with
individual product-term allocation
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Local clock inversion with three global and one
product-term clocks
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Individual output enable per output pin
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Input hysteresis on all user and boundary-scan pin
inputs
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Bus-hold ciruitry on all user pin inputs
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Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
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20 year data retention
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ESD protection exceeding 2,000V
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. PIO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. ICCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
ICCINT (taken from simulation) is:
ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG
where:
MCHS = # macrocells used in high speed mode
MCLP = #macrocells used in low power mode
PTHS = average p-terms used per high speed macrocell
PTLP = average p-terms used over low power macrocell
fMAX = max clocking frequency in the device
MCTOG = % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95288XV High-Performance
CPLD
DS050 (v3.0) June 25, 2007
05
Product Specification
R
相关PDF资料 |
PDF描述 |
|---|---|
| XC95288XV | High-Performance CPLD |
| XCA1A | POWER/SIGNAL RELAY, SPDT, MOMENTARY, 0.056A (COIL), 28VDC (COIL), 1568mW (COIL), 10A (CONTACT), 28VDC (CONTACT), SOCKET MOUNT |
| XCA1N | POWER/SIGNAL RELAY, SPDT, MOMENTARY, 0.056A (COIL), 28VDC (COIL), 1568mW (COIL), 10A (CONTACT), 28VDC (CONTACT), SOCKET MOUNT |
| XCD1N | POWER/SIGNAL RELAY, SPDT, MOMENTARY, 0.056A (COIL), 28VDC (COIL), 1568mW (COIL), 10A (CONTACT), 28VDC (CONTACT), SOCKET MOUNT |
| XCD2A | POWER/SIGNAL RELAY, SPDT, MOMENTARY, 0.056A (COIL), 28VDC (COIL), 1568mW (COIL), 10A (CONTACT), 28VDC (CONTACT), PANEL MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC95288XV-7PQ208I | 制造商:XILINX 制造商全称:XILINX 功能描述:High-Performance CPLD |
| XC95288XV-7TQ144C | 功能描述:IC CPLD 2.5V ISP 144-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:XC9500XV 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| XC95288XV-7TQ144I | 制造商:Xilinx 功能描述: |
| XC95288XVSERIES | 制造商:XILINX 制造商全称:XILINX 功能描述:High-Performance CPLD |
| XC9536 | 制造商:XILINX 制造商全称:XILINX 功能描述:XC9536 In-System Programmable CPLD |
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