参数资料
型号: XCS05-3VQ100I
厂商: Xilinx Inc
文件页数: 54/83页
文件大小: 0K
描述: IC FPGA 5V I-TEMP 100-VQFP
产品变化通告: Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010
标准包装: 90
系列: Spartan®
LAB/CLB数: 100
逻辑元件/单元数: 238
RAM 位总计: 3200
输入/输出数: 77
门数: 5000
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 100-TQFP
供应商设备封装: 100-VQFP(14x14)
Spartan and Spartan-XL FPGA Families Data Sheet
58
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan-XL Family Output Flip-Flop, Clock-to-Out
Symbol
Description
Device
Speed Grade
Units
-5
-4
Max
Global Clock to Output using OFF
TICKOF
Fast
XCS05XL
4.6
5.2
ns
XCS10XL
4.9
5.5
ns
XCS20XL
5.2
5.8
ns
XCS30XL
5.5
6.2
ns
XCS40XL
5.8
6.5
ns
Slew Rate Adjustment
TSLOW
For Output SLOW option add
All Devices
1.5
1.7
ns
Notes:
1.
Output delays are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.
3.
OFF = Output Flip Flop
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