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| 型号： | XCS20XL-3BG208I |
| 厂商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴达和Spartan - xL的家庭现场可编程门阵列 |
| 文件页数： | 22/82页 |
| 文件大小： | 863K |
| 代理商： | XCS20XL-3BG208I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Express Mode (Spartan-XL only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers (Figure 27). A CCLK fre-
quency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the devel-
opment system. The Express mode bitstream is not com-
patible with the other configuration modes (see Table 16,
page 32.) Express mode is selected by a <0X> on the Mode
pins (M1, M0).
The first byte of parallel configuration data must be available
at the D inputs of the FPGA a short setup time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(Figure 28).
Pseudo Daisy Chain
Multiple devices with different configurations can be config-
ured in a pseudo daisy chain provided that all of the devices
are in Express mode. A single combined bitstream is used
to configure the chain of Express mode devices. CCLK pins
are tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. Frame
data is accepted only when CS1 is High and the device’s
configuration memory is not already full. The lead device in
the chain has its CS1 input tied High (or floating, since there
is an internal pull-up). The status pin DOUT is pulled Low
after the header is received by all devices, and remains Low
until the device’s configuration memory is full. DOUT is then
pulled High to signal the next device in the chain to accept
the configuration data on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
to the DONE pin. User I/Os for each device become active
Figure 26: Slave Serial Mode Programming Switching Characteristics
TCCH
Bit n
Bit n + 1
Bit n
Bit n – 1
TCCO
TCCL
TCCD
TDCC
DIN
CCLK
DOUT
(Output)
DS060_26_080400
Symbol
Description
Min
Max
Units
TDCC
CCLK
DIN setup
20
-
ns
TCCD
DIN hold
0
-
ns
TCCO
DIN to DOUT
-
30
ns
TCCH
High time
40
-
ns
TCCL
Low time
40
-
ns
FCC
Frequency
-
10
MHz
Notes:
1.
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are
High.
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相关代理商/技术参数 |
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