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参数资料
| 型号： | XCV405E-6FG676I |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | FPGA, 2400 CLBS, 129600 GATES, 357 MHz, PBGA676 |
| 封装： | PLASTIC, FBGA-676 |
| 文件页数： | 17/20页 |
| 文件大小： | 191K |
| 代理商： | XCV405E-6FG676I |
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
DS025-3 (v2.3.2) March 14, 2003
6
1-800-255-7778
R
IOB Input Switching Characteristics Standard Adjustments
I
Speed Grade(1)
Units
Description
Symbol
Standard
Min
-8
-7
-6
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
TILVTTL
LVTTL
0.0
ns
TILVCMOS2
LVCMOS2
–0.02
0.0
ns
TILVCMOS18
LVCMOS18
–0.02
+0.20
ns
TILVDS
LVDS
0.00
+0.15
ns
TILVPECL
LVPECL
0.00
+0.15
ns
TIPCI33_3
PCI, 33 MHz, 3.3 V
–0.05
+0.08
ns
TIPCI66_3
PCI, 66 MHz, 3.3 V
–0.05
–0.11
ns
TIGTL
GTL
+0.10
+0.14
ns
TIGTLPLUS
GTL+
+0.06
+0.14
ns
TIHSTL
HSTL
+0.02
+0.04
ns
TISSTL2
SSTL2
–0.04
+0.04
ns
TISSTL3
SSTL3
–0.02
+0.04
ns
TICTT
CTT
+0.01
+0.10
ns
TIAGP
AGP
–0.03
+0.04
ns
Notes:
1.
Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Figure 1: Virtex-E Input/Output Block (IOB)
OBUFT
IBUF
Vref
ds022_02_091300
SR
CLK
ICE
OCE
O
I
IQ
T
TCE
D
CE
Q
SR
D
CE
Q
SR
D
CE
Q
SR
PAD
Programmable
Delay
Weak
Keeper
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV405E-6FG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG556C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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